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11 of up to 20 (filtered)

Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics

San Jose, CA 2 days ago $124,000–$208,400
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Synthesis Linting Timing Analysis Microarchitecture PPA Digital Design Fixed-Function Logic Memory Systems
2+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 39 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification Machine Learning
10+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 39 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification Machine Learning
3+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
ASIC Design RTL Verilog System Verilog SoC Digital Design Synthesis Python Perl TCL AMBA AXI AHB APB power-gating CDC RDC Logic Equivalence Check Formal Verification
10+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
Verilog System Verilog RTL ASIC Design SoC Synthesis AMBA AXI AHB APB Python Perl TCL CDC RDC Logic Equivalence Check Linting Formal Verification Digital Signal Processing power-gating
3+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 44 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Python Perl TCL SystemC C++ High-Level Synthesis Synthesis Power Analysis Finite State Machines
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 155 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification Machine Learning Interconnects Memory Controllers Address Translation Caching
10+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 155 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification Machine Learning Interconnects Memory Controllers Address Translation Caching
3+ yrs exp
Save

ASIC Design Engineer, Pixel IP DMA

Apple Inc

Cupertino, CA 155 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Formal Verification Power Analysis Machine Learning Interconnects Memory Controllers Address Translation Caching
3+ yrs exp
Save

ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 155 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Area and Power Analysis Formal Verification Machine Learning Image Processing Interconnects Memory Controllers
Save

ASIC Design Engineer, Pixel IP DMA

Apple Inc

Cupertino, CA 155 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
RTL Design ASIC Design DMA Engines AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification SoC Machine Learning Image Processing Interconnects Memory Controllers
Save