ASIC Design Engineer, Pixel IP DMA

Apple Inc

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
171 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $214k
$135k $293k
below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $168,500–$229,650 — the blue band above. At the midpoint, this role pays about $214k versus about $199k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Pixel IP DMA

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ASIC Design Engineer - Pixel IP DMA will join the Hardware Technologies group to design high-performance, power-efficient system-on-chips. In this front-end design role, you will work with architecture, design, and verification teams to build DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine. Your daily responsibilities include exploring solutions to enhance performance while minimizing power and area, detailing specifications, and building RTL designs. You will also collaborate with verification teams to verify functionality and performance. Required skills include experience in multimedia IP or SoC front-end ASIC RTL design, knowledge of AMBA protocols like AXI, AHB, and APB, and familiarity with synthesis, linting, and logic equivalence checks. The role focuses on solving data movement challenges for pixel processing.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Formal Verification Power Analysis Machine Learning Interconnects Memory Controllers Address Translation Caching

What you'll do

  • Build high-performance and low-power DMA engines to move data between memory systems and the Pixel IP Engine.
  • Explore technical solutions to enhance performance while minimizing power consumption and silicon area.
  • Detail technical specifications and develop RTL designs for front-end ASIC implementation.
  • Work with verification teams to validate functionality and performance through design and formal verification.
  • Perform front-end implementation tasks including synthesis, linting, and logic equivalence checks.
  • Conduct area and power analysis to ensure design efficiency.
  • Analyze performance metrics related to arbitration, address translation, caching, and on-chip interconnects.

What we're looking for

  • 3 years of experience.
  • Experience in multimedia IP/SoC front-end ASIC RTL design (preferred).
  • Tight-knit collaboration skills with excellent written and verbal communication skills (preferred).
  • Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs (preferred).
  • Previous experience designing dedicated DMA engines, data storage, memory controllers, networking, image processing, and/or interconnects (preferred).
  • Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis (preferred).
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
  • Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks (preferred).

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