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TCL Perl Python Cadence_Innovus Synopsys_ICC2 Synopsys_Design_Complier Synopsys_Formality Cadence_Logic_Equivalence_Checker Tempus Synopsys_ICV Mentor_Calibre Static_Timing_Analysis Hierarchical_floor_planning Clock_and_power_distribution Global_signal_and_I_O_planning Physical_verification_DRC/LVS Block_level_EMIR_closure ECO_strategies RTL_to_GDSII_implementation +14 more Show less

C++ Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC VLSI EDA Multithreading Distributed computing Reinforcement learning GNNs Graph Neural Networks CI/CD +12 more Show less

C++ Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC VLSI Reinforcement Learning GNNs Graph Neural Networks Multithreading Distributed Computing CI/CD +11 more Show less

Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD +5 more Show less

TCL PERL EDA Tools RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +6 more Show less

TCL PERL EDA Tools RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +6 more Show less

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PTPX ICC Calibre Sonata QCAT Qualcomm SNAP Linux Git JIRA Confluence +15 more Show less

C C++ Python Perl Verilog VHDL UVM SystemC DVFlow CI/CD Linux +6 more Show less

C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Tensilica Instruction Extension (TIE) Linux +8 more Show less

Synopsys_Fusion_Compiler Synopsys_ICC2 Cadence_Genus Cadence_Innovus Python Perl TCL Shell_Scripting Timing_Analysis Physical_Design Clock_Tree_Synthesis Power_Optimization Logic_Optimization ASIC_Physical_Design CI/CD +10 more Show less

C++ Python ICCAD tools Innovus Computational geometry Graph theory Algorithm development Multithreading Distributed computing High performance software design GUI development Machine learning VLSI Physical Design +8 more Show less

Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ Tcl Unix/Linux Cadence Synopsys Mentor Graphics ASIC Design Design Verification CI/CD Git +10 more Show less

TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction +10 more Show less

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PT PowerAware ICC/Innovus Calibre Synopsys DC Cadence Genus ModelSim/QuestaSim Linux Git JIRA Confluence +15 more Show less

Verilog RTL Synthesis Place_and_Route Timing_Analysis Power_Analysis GDS CPU_Microarchitecture Library_Cells High_Performance_Implementation Low_Power_Implementation Tapeout_Flows +7 more Show less

SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clocking_Solutions HDL Verilog SystemVerilog Cadence Synopsys Calibre +15 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less