Browse tech roles

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

Physical Design CAD Tools Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI SoC Design Signoff Physical Verification +9 more Show less

PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis +14 more Show less

Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT +20 more Show less

Physical Design Silicon Design Synthesis Place and Route Clock Construction CTS Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification RTL to GDS PPA Floorplanning Extraction Tape-out +11 more Show less

Physical Design Synthesis Place and Route Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification Clock Construction CTS RTL to GDS PPA Semiconductor Design Tape-out Floorplanning Extraction +11 more Show less

VLSI Physical Design RTL2GDS Place and Route Timing Closure Power and Clock Distribution Physical Verification IR Drop Analysis RC Extraction Synopsys (ICC2 Cadence (Genus Python Perl Tcl Make ML AI +11 more Show less

Static Timing Analysis (STA) Synthesis ECO Physical Design RTL Python Tcl Make Synopsys PrimeTime Cadence Tempus Logical Equivalence Checking (LEC) DFT Floor-planning Routing Noise Analysis +10 more Show less

ASIC SoC Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python Perl TCL C/C++ Shell Scripting Linux Unix Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis +14 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

Python Tcl ML Frameworks Physical Design P&R Timing Analysis IR/Signal-EM Power and Noise Analysis Back-end Verification Chip Floorplan Power and Clock Distribution PPA +7 more Show less

Physical Design ASIC Design Flow Synthesis Place and Route Clock Tree Synthesis floor planning TCL Perl Shell Python DFM Signal Integrity FinFET +8 more Show less

Physical Design Synthesis place-and-route Timing Closure Signoff Python TCL Shell Perl ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC Calibre ICV DRC LVS DTCO +15 more Show less

GPU Physical Design SoC Design Synthesis place-and-route Clock Tree Synthesis Timing Closure Signoff STA DRC LVS Python Tcl Shell Perl ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC DTCO +16 more Show less

GPU Physical Design Place-and-Route Floorplanning Timing Closure STA Power-Grid Design DRC LVS FusionCompiler Innovus ICC2 PrimeTime Tempus StarRC RedHawk Python Tcl Shell Perl DTCO PPA Physical Verification Clock Tree Synthesis Synthesis +19 more Show less

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design +10 more Show less

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design +10 more Show less

VLSI Physical Design P&R Timing Closure Static Timing Analysis IR Drop Analysis Physical Verification RC Extraction Python Perl Tcl Make Synopsys (ICC2 Cadence (Innovus Mentor Graphics ASIC Power Distribution Clock Distribution +12 more Show less

RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks +14 more Show less