CPU Server Physical Design Clock Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$148,300–$222,500 / yr
Posted
24 days ago
Closes
Nov 17, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $185k
$137k most similar roles pay here $252k

This role pays less than 59% of similar roles. Most pay $169,875–$225,600 — the shaded band above. At the midpoint, this role pays about $185k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 750 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 430 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Clock Engineer

As a Physical Design Clock Engineer at Qualcomm Technologies, you will collaborate with microarchitecture, RTL design, CAD, and physical design teams to develop cutting-edge clocking solutions for next-generation CPUs. Your daily responsibilities include constructing low skew and low power clock generation and distribution systems, implementing H-tree, mesh, spines, and CTS designs, and conducting SPICE simulations for circuit verification. You will define clock methodologies across various CPU designs, optimize standard cell configurations, and work closely with CAD and block level designers to minimize clock skew and power consumption. Proficiency in deep submicron process technology nodes, PLL specifications, and jitter analysis is essential, as you will drive the overall clock generation methodology and provide critical feedback for design improvements. This role requires a strong background in electrical engineering and extensive experience in chip physical design, making it ideal for those with a passion for advanced semiconductor technologies.

What you'll do

  • Analyze and implement low skew and low power clock generation and distribution.
  • Design and optimize H-tree, mesh, spines, and CTS implementations for CPUs.
  • Conduct SPICE simulations to verify circuit designs and ensure electrical integrity.
  • Define and drive overall clock methodology for CPU design across various teams.
  • Perform jitter analysis and provide feedback on necessary fixes for clocking issues.

What we're looking for

  • Experience in low skew and low power clock generation and distribution.
  • Proficiency in clock H-tree, mesh, spines, and CTS implementations.
  • Understanding of device physics, RC delay, and electrical aspects.
  • SPICE simulation and analysis for circuit design and verification skills.
  • MS in Electrical Engineering with 8+ years of practical experience.
  • Defined clock methodology across various designs and process nodes.
  • Strong communication skills for team collaboration and issue resolution.

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