As a Senior R&D Software Engineer on NVIDIA's cutting-edge hardware development team, you will focus on inventing new optimization engines that integrate traditionally separate processes like legalization and sizing to enhance chip frequency while reducing power consumption. Your daily tasks include refining algorithms in C++ for gate-level sizing, buffering, clock skew management, cell legalization, and incremental parasitic extraction across a suite of internal tools. This role demands expertise in VLSI physical design algorithms, proficiency with C++14 or newer standards, and familiarity with industry-leading EDA tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC. Additionally, experience with high-performance software design principles, including multithreading and distributed computing, is essential, along with a passion for continuous improvement in physical design optimization.
Invent new optimization engines that integrate multiple independent tools for better chip performance.
Enhance algorithms for gate-level sizing, buffering, clock skew management, cell legalization, power minimization, ECO routing, and parasitic extraction.
Develop high-performance software using C++14 or newer features like lambdas and concurrency.
Explore fusion of Physical Design steps to create hybrid engines that improve PPA (Power, Performance, Area).
Work directly with design teams to facilitate the deployment of new optimization solutions.
Continuously refine and optimize software for superior power efficiency and performance.
What we're looking for
Proven experience in VLSI Physical Design Algorithms development using C++ for at least 6 years.
Strong understanding of VLSI timing optimization concepts, including cell libraries and interconnect models.
Familiarity with design implementation tools like ICC2, Innovus, PrimeTime, Tempus, and StarRC.
Experience in high-performance software design, including multithreading and distributed computing.
Detailed knowledge of how Physical Design steps interact to form hybrid engines improving PPA.
Dedication to continuous improvement and crafting outstanding software for better PPA.
Familiarity with reinforcement learning, GNNs, and other machine learning frameworks applied to physical design.
Market check
Salary context
Above market
How this pay compares to similar roles
Similar $175k
This role $216k
$120k
most similar roles pay here
$280k
This role pays more than
85%
of similar roles. Most pay
$144,875–$205,000
— the shaded band above.
At the midpoint, this role pays about
$216k
versus about
$175k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
824 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 812 roles with salary data.
C++
Python
ICCAD tools
Innovus
Computational geometry
Graph theory
Algorithm development
Multithreading
Distributed computing
High performance software design
GUI development
Machine learning
VLSI Physical Design
C++
Verilog
SystemVerilog
EDA
RTL synthesis
digital logic optimization
graph-based algorithms
AI
ML
GNNs
RL
DFT
clock distribution
power gating
placement
congestion
timing analysis
SAT solvers
technology mapping
clustering
min cost tree covering
high performance computing
multithreading
distributed computing
SystemVerilog
UVM
Python
TcL
Perl
Cadence Genus
Cadence Conformal
Cadence Innovus
Cadence Voltus
Cadence Tempus
Cadence Modus
Low power design methods
DSP
Digital Analog Boundary (DAB) crossings
A2D
D2A
Lab automation methods
Agentic AI