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Active Keyword: Memory IC Design Remove filter Clear all

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High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
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Design Verification Engineer, DDR Memory Subsystem

Microsoft

25 days ago $102,100–$202,200
Actively hiring Confirmed live 2 days ago Trusted Below market
UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI JEDEC Memory Controller Generative AI Verification Methodology
2+ yrs exp
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Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 25 days ago $153,200–$229,800
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis
4+ yrs exp
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 30 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 37 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Low trust Below market
Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems
4+ yrs exp
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Senior Design Verification Engineer, GPU Memory Subsystem

Nvidia

Durham, NC 144 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Low trust Competitive pay
System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification
5+ yrs exp
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