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Active Keyword: Memory IC Design Remove filter Clear all

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Senior ASIC Design Engineer, Memory Subsystem

Nvidia

Santa Clara, CA 14 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces
5+ yrs exp
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Senior Design Verification Engineer, GPU Memory Subsystem

Nvidia

Durham, NC 20 days ago $136,000–$218,500
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures
5+ yrs exp
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Design Verification Engineer, DDR Memory Subsystem

Microsoft

27 days ago $102,100–$202,200
Actively hiring Confirmed live yesterday Trusted Below market
UVM System Verilog Formal Verification Python PCIe CXL AMBA CHI JEDEC Memory Controller IP Verification Generative AI Simulation SVTB
2+ yrs exp Hybrid
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Lead Design Verification Engineer, Memory Controller

Amd

San Jose, CA 35 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management
8+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 40 days ago $159,600–$239,400
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation
4+ yrs exp
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Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture
4+ yrs exp
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