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Senior Memory Controller Verification Engineer

Nvidia

Santa Clara, CA 3 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago Posted this week High trust Competitive pay
System Verilog UVM VCS C C++ Python Perl Shell ASIC Verification RTL FPGA Debussy GDB DDR LPDDR
3+ yrs exp Hybrid
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High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
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Staff Memory Controller Architecture and Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC
4+ yrs exp
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Senior Memory Controller Verification Engineer

Nvidia

Santa Clara, CA +4 50 days ago $168,000–$264,500
Actively hiring Confirmed live 2 days ago Trusted Above market
System Verilog UVM VCS C++ C Python Perl Shell FPGA RTL Post-silicon Verification DDR LPDDR HBM GDDR GDB Debussy
6+ yrs exp Hybrid
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