Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

8 of up to 20 (filtered)

Senior High-Speed I/O Engineer

Apple Inc

Cupertino, CA 2 days ago $184,700$324,800
Actively hiring Confirmed live yesterday Posted this week High trust Above market
High-Speed I/O USB Thunderbolt HDMI DisplayPort PCIe C Objective-C Lua Signal Integrity Firmware Scripting Root Cause Analysis Statistical Analysis Gauge R&R
7+ yrs exp

ARM Server Platform I/O & Interconnect Software Architect

Qualcomm

Santa Clara, CA +4 29 days ago $211,800$317,800
Actively hiring Confirmed live 2 days ago High trust Above market
ARM PCIe CXL Linux Kernel UEFI EDK2 Arm Trusted Firmware OpenBMC KVM Hypervisors C C++ Python IOMMU SMMU ACPI RAS Confidential Computing Firmware
8+ yrs exp

Senior High-Speed I/O Engineer

Apple Inc

Cupertino, CA 31 days ago $184,700$324,800
Actively hiring Confirmed live yesterday High trust Above market
High-Speed I/O Signal Integrity C Objective-C Lua USB Thunderbolt HDMI DisplayPort PCIe Firmware Scripting Root Cause Analysis Statistical Analysis Gauge R&R
7+ yrs exp

Senior SoC Subsystem and I/O Architect

Nvidia

Remote (CA) +2 36 days ago $184,000$287,500
Actively hiring Confirmed live yesterday High trust Above market
SoC Architecture PCIe CXL NVLink UCIe AXI CHI NoC SystemC C++ Python Memory Systems Virtualization IOMMU Firmware Boot Power Management RAS DFT
8+ yrs exp Remote

Staff Engineer, High-Speed I/O Analog-Mixed Circuit

Samsung Semiconductor

San Jose, CA 44 days ago $163,000$253,000
Actively hiring Confirmed live yesterday High trust Above market
Analog Circuit Design Mixed-Signal Design SERDES PLL DDR LPDDR GDDR HBM CMOS Cadence MATLAB Simulink Tcl Perl Python EDA Tools Silicon Bring-up
10+ yrs exp

Senior I/O Subsystem Architect

Nvidia

Santa Clara, CA 50 days ago $224,000$356,500
Actively hiring Confirmed live 2 days ago High trust Above market
NVLink PCIe UCIe CHI CXL AXI I/O Architecture Link Layer Transaction Layer Data Link Layer Physical Layer SoC Firmware
10+ yrs exp Hybrid

Senior Digital Design Engineer, High-Speed I/O and Photonics

Nvidia

Santa Clara, CA 95 days ago $136,000$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog System Verilog RTL UVM SerDes Ethernet InfiniBand PCIe USB Silicon Photonics Static Timing Analysis Synthesis Firmware Co-Packaged Optics CDR DFE CTLE
5+ yrs exp Hybrid

Senior ASIC Design Engineer, Ethernet Switch & High-Speed I/O

Amd

Santa Clara, CA 115 days ago $200,000$300,000
Actively hiring Confirmed live 2 days ago High trust Above market
RTL Design SystemVerilog Verilog Ethernet SerDes VCS Python Perl Shell Scripting ASIC Design Switch Fabric Queue Management High-speed I/O Post-silicon Bring-up