I/O Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Chandler, AZ
Salary
$109,700–$175,500 / yr
Employment
Full-time
Posted
62 days ago
Freshness
Confirmed live yesterday
Closes
Jan 7, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k
This role $143k
$94k $258k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $162,000–$241,750 — the blue band above. At the midpoint, this role pays about $143k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 241 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · I/O Design Engineer

Role Posting Log in to save

The I/O Design Engineer joins the Central Engineering Group to contribute to the design and verification of a broad range of IP and I/Os, specifically for leading-edge AI programs on advanced nodes. The role involves designing CMOS I/O, high-precision bandgap references, op-amps, comparators, and power-on-reset circuits. Daily tasks include running simulations to validate AC/DC performance, signal integrity, jitter, and power, alongside performing transistor reliability and EMIR analysis. The engineer will build Verilog, Synopsys Liberty, and IBIS models while overseeing physical design with layout teams. Required expertise includes Cadence Virtuoso Schematic/Layout capture, SPICE/Spectre simulation, and protocols like GPIO, I2C, I3C, eMMC, RGMII, and SPMI. The position requires deep knowledge of advanced CMOS FinFET and GAA process nodes and PPA tradeoffs.

Skills

Mixed-Signal IC Design CMOS Cadence Virtuoso SPICE Spectre Verilog Synopsys Liberty IBIS GPIO I2C I3C eMMC RGMII SPMI FinFET GAA Signal Integrity EMIR ESD Latch-up

What you'll do

  • Design CMOS I/O, high-precision bandgap references, op-amps, comparators, and power-on-reset circuits.
  • Run simulations to validate AC/DC performance, signal integrity, jitter, and power.
  • Perform transistor reliability and EMIR analysis.
  • Oversee physical design and verification in close coordination with layout teams.
  • Build Verilog, Synopsys Liberty, and IBIS models.
  • Create and maintain technical documentation, including datasheets, application notes, and integration guides.
  • Support chip-level integration and silicon bring-up in test chips and customer products.

What we're looking for

  • MS or PhD in Electrical Engineering.
  • 6+ years of I/O or analog circuit design experience.
  • Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
  • Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.
  • Familiarity with ESD, Latch-up, EMI and Signal Integrity.
  • Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.
  • Experience designing CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits.
  • Ability to build Verilog, Synopsys Liberty and IBIS models.

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