Senior SoC Subsystem and I/O Architect

What you'll do

• Define high-level SoC subsystem architecture for LPU products.
• Convert product requirements into architectural specifications for uncore, I/O, memory, and power regulation subsystems.
• Develop detailed build documents for PCIe/CXL, NVLink, UCIe, AXI/CHI, and NoC fabrics with IP teams.
• Specify subsystem behaviors including enumeration, configuration flows, data consistency, and interrupt handling.
• Build and guide functional and architectural models using C++, SystemC, or Python to validate architecture intent.
• Drive technical tradeoffs across bandwidth, latency, power, area, timing, scalability, and reliability.
• Review IP specifications, architecture documents, verification plans, and validation strategies.
• Harmonize architecture decisions across firmware, software, RTL, and post-silicon teams.

What we're looking for

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years of proven experience in SoC, subsystem, IO, interconnect, GPU/CPU, accelerator, or high-performance systems architecture.
• Strong understanding of SoC architecture and uncore subsystem development.
• Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics.
• Experience converting product requirements into architecture requirements and IP/subsystem specifications.
• Experience crafting functional, architectural, or golden models using C++, SystemC, Python, or similar languages.
• Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management.
• Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture.