Senior SoC Subsystem and I/O Architect

What you'll do

• Define high-level SoC subsystem architecture for LPU products based on product requirements.
• Convert product requirements into technical specifications for uncore, I/O, memory, and power management subsystems.
• Collaborate with IP teams to develop detailed build documents for PCIe, CXL, NVLink, and NoC fabrics.
• Specify subsystem behaviors including enumeration, configuration flows, data consistency, and interrupt handling.
• Build or guide the creation of functional and architectural models using C++, SystemC, or Python.
• Use architectural models to validate intent, behavior, and IP interactions before RTL or silicon is available.
• Drive technical tradeoffs across bandwidth, latency, power, area, timing, and software usability.
• Review IP specifications, architecture documents, verification plans, and validation strategies.

What we're looking for

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years of proven experience in SoC, subsystem, IO, interconnect, GPU/CPU, accelerator, or high-performance systems architecture.
• Extensive knowledge of uncore subsystems and interconnects including PCIe, CXL, NVLink, UCIe, AXI, CHI, and NoC fabrics.
• Experience converting product requirements into architectural specifications for memory, firmware, boot, power management, and safety systems.
• Proficiency in building functional or architectural models using C++, SystemC, Python, or similar languages.
• Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, and error management.
• Knowledge of boot architecture, reset sequencing, secure boot, RAS, debug, DFT, and power sequencing.
• Strong communication skills to harmonize architectural decisions across IP, firmware, software, verification, and product teams.