Principal High-Speed I/O Architect

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CASeattle, WA
Salary
$262,700–$355,400 / yr
Posted
165 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $221k
This role $309k
$153k most similar roles pay here $377k

This role pays more than 95% of similar roles. Most pay $187,850–$254,750 — the shaded band above. At the midpoint, this role pays about $309k versus about $221k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 106 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 106 roles with salary data.

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View all roles at Arm Holdings

At a glance

TL;DR · Principal High-Speed I/O Architect

As a Principal High-Speed I/O Architect, you will join the team to define and design innovative coherent and non-coherent on-chip interconnect architectures for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets. You will be responsible for architecting high-speed interconnect subsystems including PCIe, CXL, and UA Link while defining IP and subsystem roadmaps in partnership with core technology teams. Your daily work involves leading early architecture engagements with customers to shape requirements, collaborating with performance and physical design teams to optimize bandwidth and latency, and developing SoC architectures that integrate Arm IP to meet specific memory and interconnect targets. You will utilize deep expertise in coherency protocols, hierarchical cache design, and transaction flows to solve complex problems involving memory expansion, pooling, and die-to-die connectivity within high-performance semiconductor environments.

What you'll do

  • Architect high-speed interconnect subsystems including PCIe, CXL, and UA Link for coherent and non-coherent communication.
  • Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in partnership with core teams.
  • Lead early architecture engagements with customers to shape system requirements and deliver implementation-ready specifications.
  • Optimize bandwidth, latency, and power efficiency for PCIe, CXL, and UA Link subsystems.
  • Integrate Arm IP and high-speed I/O subsystems into SoC architectures to meet performance targets.
  • Partner with software and firmware teams to optimize end-to-end solutions across hardware and system software.
  • Perform workload analysis and performance modeling to guide critical architectural decisions.

What we're looking for

  • Bachelor's or Master's degree in Electrical or Computer Engineering (or equivalent).
  • 10+ years of experience in semiconductor architecture, design, or related roles.
  • 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
  • Deep expertise in PCIe, CXL, and UA Link protocols including link behavior, transaction flows, and memory expansion.
  • Proven track record collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack.
  • Strong knowledge of heterogeneous compute, security, caching, and memory systems.
  • Demonstrated communication and leadership skills to influence executive stakeholders and multi-functional teams.
  • Ability to thrive in dynamic environments and a track record of delivering complex projects (preferred).

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