Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

11 of up to 20 (filtered)

Senior High Speed SerDes Validation Engineer

Nvidia

Santa Clara, CA 6 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
GPU C C++ Python SERDES High speed IO Oscilloscopes Waveform Analysis Ethernet InfiniBand Deep Learning AI System Management
6+ yrs exp

Senior Leader, Electrical Systems Architect

Qualcomm

San Diego, CA 12 days ago $256,600–$385,000
Actively hiring Confirmed live yesterday High trust Above market
PAM4 SerDes Signal Integrity (SI) Power Integrity (PI) PCB Design Advanced Packaging ADS HFSS CST HSPICE MATLAB Python Cadence Sigrity PowerSI Clarity SystemVerilog Verilog-A IBIS-AMI Ethernet PCIe UALink NVLink
10+ yrs exp

Senior High-Speed I/O Engineer

Apple Inc

Cupertino, CA 24 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
High-Speed I/O USB Thunderbolt HDMI DisplayPort PCIe C Objective-C Lua Signal Integrity Firmware Scripting Root Cause Analysis Statistical Analysis Gauge R&R
7+ yrs exp

Senior High-Speed I/O Engineer

Apple Inc

Cupertino, CA 53 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
High-Speed I/O Signal Integrity C Objective-C Lua USB Thunderbolt HDMI DisplayPort PCIe Firmware Scripting Root Cause Analysis Statistical Analysis Gauge R&R
7+ yrs exp

PCIe, CXL and Highspeed IO Validation Engineer

Amd

Austin, TX +1 67 days ago $194,400–$291,600
Actively hiring Confirmed live yesterday High trust Above market
PCIe CXL UCIe Python C/C++ Perl Linux Windows Post-Silicon Validation root-cause analysis Logic Analyzers Oscilloscopes System Architecture High-Speed IO
7+ yrs exp Hybrid

High Speed IO Analog Mixed Signal Design Engineer

Amd

San Jose, CA 71 days ago $216,000–$324,000
Actively hiring Confirmed live yesterday High trust Above market
SerDes High-Speed IO LPDDRx gDDRx HBM3 PCIe USB PLL DLL Clock Distribution Spectre HSPICE FinFET CMOS Circuit Simulation Link Budget Analysis
Hybrid

Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Santa Clara, CA 74 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday High trust Above market
Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Power Optimization Performance Analysis Chiplets NVLINK-C2C
8+ yrs exp Hybrid

Senior Digital Design Engineer, High-Speed I/O and Photonics

Nvidia

Santa Clara, CA 118 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog System Verilog RTL UVM SerDes Ethernet InfiniBand PCIe USB Silicon Photonics Static Timing Analysis Synthesis Firmware Co-Packaged Optics CDR DFE CTLE
5+ yrs exp Hybrid