PCIe, CXL and Highspeed IO Validation Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TXSanta Clara, CA
Salary
$194,400–$291,600 / yr
Posted
45 days ago
Freshness
Confirmed live yesterday
Closes
Jul 28, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $187k
This role $243k
$118k most similar roles pay here $310k

This role pays more than 89% of similar roles. Most pay $159,750–$214,000 — the shaded band above. At the midpoint, this role pays about $243k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · PCIe, CXL and Highspeed IO Validation Engineer

The PCIe, CXL and Highspeed IO Validation Engineer joins the datacenter CPU post silicon validation team to focus on highspeed IO such as PCI Express, Compute Express Link, multi-socket, and inter-die interfaces. This principal role involves developing and executing feature enablement and validation test plans for SoC and system-level features across server products. The engineer will build post-silicon validation infrastructure including software, hardware, and automation environments while performing root-cause analysis for SoC issues. Key responsibilities include creating test content for focus and stress testing and collaborating with cross-functional teams to improve validation methodologies. Required expertise includes PCIe Gen5/6+, CXL, UCIe, and x86 microprocessor architecture. Technical skills include proficiency in C/C++, Python, or Perl, knowledge of Linux and Windows operating systems, and experience using protocol analyzers and oscilloscopes for board-level debug.

What you'll do

  • Develop and execute feature enablement and validation test plans for high-speed IO across all server products.
  • Create test content for focused testing and system-level stress testing of the IO domain.
  • Build post-silicon validation infrastructure including software, hardware, automation environments, and lab setups.
  • Test interactions between various SoC features using specialized validation infrastructure.
  • Perform root-cause analysis to debug and resolve SoC-related issues.
  • Develop tools in collaboration with cross-functional teams to improve SoC validation and debugging.
  • Improve post-silicon validation test strategies, methodologies, and processes.

What we're looking for

  • A Bachelor's degree in BSEE/CSE/CS with 7+ years of experience is required.
  • A Master's degree in MSEE/CSE/CS with 5+ years of experience is required.
  • Proven hands-on experience in SoC design or validation of high-speed IO interfaces.
  • Experience with PCIe Gen5/6+, CXL, UCIe, or proprietary inter-die and multi-socket server interfaces.
  • Understanding of modern x86 microprocessor architecture and Server platform architecture.
  • Proficiency in programming or scripting languages such as C/C++, Python, or Perl.
  • Extensive experience with lab equipment including protocol/logic analyzers and oscilloscopes.
  • Experience in board/platform-level debug, including delivery, sequencing, analysis, and optimization.

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