Quick summary
- Work type
- On-site
- Location
- —
- Salary
- $136,000–$212,750 / yr
- Employment
- Full-time
- Posted
- 118 days ago
- Freshness
- Confirmed live yesterday
Market check
Salary context
Below market
How this pay compares to similar roles
Similar $199k
This role $174k
$124k
most similar roles pay here
$244k
This role pays less than 72% of similar roles. Most pay $169,625–$227,900 — the shaded band above. At the midpoint, this role pays about $174k versus about $199k for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has 1371 open roles on FindRole.
Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.
Most-posted roles
- Software Engineer 122
- Solutions Architect 76
- System Software Engineer 74
- Systems Software Engineer 30
- Developer Relations Manager 27
At a glance
TL;DR · Senior High-Speed IO Validation Engineer
The Senior High-Speed IO Validation Engineer joins the hardware product team to manage end-to-end HSIO validation for GPU, CPU, and high-performance computing platforms. This role involves developing test plans, automation, and coverage metrics while performing system-level debug from initial bring-up through full production. The engineer will validate critical interfaces including PCIe, NVLink, C2C, Ethernet, USB, DP, HDMI, and CXL across protocol, link, and physical layers. Key responsibilities include signal integrity characterization, link tuning, margin analysis, and reviewing board schematics and PCB layouts. Required expertise includes experience with high-bandwidth DSOs, BERTs, logic analyzers, and TDR equipment. The role addresses complex interconnect topologies and ensures specification compliance for high-speed data transmission. Candidates must possess a solid understanding of SerDes, link training, equalization, and power management to ensure robust performance across various silicon and platform configurations.
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