Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Cohere Remove filter Clear all

10 of up to 20 (filtered)

Senior Verification Engineer, High Speed Coherent Interconnect Hub

Nvidia

Santa Clara, CA 7 days ago $136,000–$218,500
Actively hiring Confirmed live today Posted this week High trust Competitive pay
SystemVerilog UVM Constrained-Random Verification Coverage-Driven Verification Python Perl Shell ASIC Verification RTL CHI AXI FPGA Emulation Coherent Interconnects
3+ yrs exp Hybrid
Save

Product Line Manager, Coherent Optical Transceivers

Cisco

Holmdel, NJ +1 7 days ago $194,600–$285,700
Actively hiring Confirmed live today Posted this week High trust Above market
Optical Communications DSP Architecture Silicon Photonics QSFP-DD OSFP 400ZR 800ZR OpenZR+ IEEE OIF LPO LRO CPO NPI Product Requirement Documents Hardware Engineering Electro-optic Characterization
10+ yrs exp Hybrid
Save

Principal Micro-architect, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 15 days ago $221,700–$364,800
Actively hiring Confirmed live today High trust Above market
RTL Design Verilog SystemVerilog ASIC Design Flow STA DFT ECO AMBA5 CHI AMBA4 ACE AXI Coherent Interconnect LLC Python Perl Computer Architecture Memory Subsystem Architecture
10+ yrs exp
Save

Staff Design Verification Engineer, Network Coherent Interconnect

Arm Holdings

Austin, TX 20 days ago $198,100–$268,000
Actively hiring Confirmed live today High trust Above market
System Verilog UVM RTL Design Python Perl Formal Verification AMBA AXI ACE CHI Microarchitecture Cache Coherence Data Structures Algorithms Object-Oriented Programming
8+ yrs exp Hybrid
Save

Staff Design Verification Engineer, Coherent Interconnect

Arm Holdings

Austin, TX 29 days ago $198,100–$268,000
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols
8+ yrs exp Hybrid
Save

Staff Design Verification Engineer, Coherent Interconnect

Arm Holdings

Austin, TX 29 days ago $198,100–$268,000
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols
8+ yrs exp Hybrid
Save

Design Verification Engineer, Coherent Interconnect

Samsung Electronics

Austin, TX +1 67 days ago $151,000–$251,800
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM Unix Perl Git UPF Gate-level Simulation Formal Verification LPDDR SoC
10+ yrs exp
Save

Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 67 days ago $151,000–$251,800
Actively hiring Confirmed live today Trusted Competitive pay
Verilog VHDL ASIC Design Flow RTL Design AMBA ACE AXI CHI STA DFT ECO Python Perl Logic Synthesis Timing Analysis Floor-planning Memory Controller Coherent Interconnect Cache Design On-chip Network Topologies
6+ yrs exp
Save

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 78 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture
5+ yrs exp
Save

Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Santa Clara, CA 97 days ago $168,000–$264,500
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Performance Analysis Power Optimization Chiplets
8+ yrs exp Hybrid
Save