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RTL Synthesis Place-and-Route Static Timing Analysis STA floor-planning PPA ECO LVS DRC EMIR Physical Design Timing Closure +8 more Show less

RTL Synthesis place-and-route PPA Logic Design Scripting Physical Design +2 more Show less

RTL Synthesis Place-and-Route PPA Digital Circuits Logic Design Scripting Programming Memory Macros Standard Cells Physical Design +6 more Show less

RTL Synthesis Place-and-Route Static Timing Analysis STA floor-planning IR Drop EMIR LVS DRC ECO PPA +7 more Show less

RTL Synthesis place-and-route Perl TCL Microarchitecture Logic Design Physical Design +3 more Show less

Synthesis PNR STA VLSI Python TCL Physical Design Logic Optimization PPA Scripting Digital Design Deep Sub-micron Technology +7 more Show less

RTL-to-GDS Synthesis place-and-route PnR PPA Optimization Clock Flow CPU Microarchitecture Physical Design Memory Design +4 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits Logic Design floor-planning Timing Budgeting Power Analysis Microarchitecture +7 more Show less

STA SPICE TCL Python Perl PnR ATPG Data Analysis Silicon Correlation Pre-silicon Design Post-silicon Debug tapeout +7 more Show less

RTL Synthesis Place-and-Route Perl TCL Microarchitecture Logic Design Physical Design +3 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits floor-planning Physical Design Power Analysis Memory Macros Standard Cells Logic Design +8 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits floor-planning Physical Design Power Analysis Logic Design Memory Macros Standard Cells +8 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits Logic Design floor-planning Timing Budgeting Power Analysis Microarchitecture +7 more Show less