CPU Implementation Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $220k

$137k most similar roles pay here $288k

This listing doesn't post a salary. Most similar roles pay $184,900–$254,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Implementation Engineer

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The CPU Implementation Engineer joins the Silicon Engineering Group to focus on block-level implementation of high-performance processor designs. In this role, you will collaborate with micro-architects to define micro-architecture and evaluate power, performance, and area trade-offs while driving RTL-to-GDS design convergence through logic optimizations. You are responsible for block-level delivery, backend flow closure, electrical requirements, and improving silicon yield. The work involves coordinating with CAD and physical design teams on synthesis and PNR tool features, as well as partnering with custom IP teams to optimize memory macros and standard cells. Key technical requirements include expertise in digital circuits, low power and high frequency design techniques, and proficiency in TCL or Perl. You will navigate complex challenges involving floorplanning, timing budgeting, and deep sub-micron technology implications for CPU microprocessor architecture.

Skills

RTL Synthesis PnR STA TCL Perl Digital Circuits floor-planning Physical Design Power Analysis Logic Design Memory Macros Standard Cells

What you'll do

Define micro-architecture and evaluate design feasibility regarding power, performance, and area trade-offs.
Drive RTL-to-GDS design convergence through logic optimizations using synthesis and place-and-route tools.
Deliver block-level designs while closing backend flows, electrical requirements, and improving silicon yield.
Collaborate with CAD and PD teams to optimize and adopt industry-standard synthesis and PNR tool features.
Coordinate with cross-functional teams on CPU floorplanning, timing, power, reliability, and testability.
Partner with custom IP teams to co-optimize memory macros and library standard cells for better PPA.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience in logic design and digital circuits.
Experience with low power and high frequency design techniques.
Experience with TCL or Perl.
Familiarity with high performance CPU microprocessor architecture and memory sub-system (preferred).
Knowledge in deep sub-micron technology and its implications to timing, power, and area (preferred).
Proficiency in industry standard logic Synthesis, PnR, STA, and Power analysis tools (preferred).
Excellent communication and interpersonal skills (preferred).