CPU Implementation Silicon Correlation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $184,700–$324,800 / yr
Posted: 16 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $213k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 92% of similar roles. Most pay $176,600–$248,781 — the shaded band above. At the midpoint, this role pays about $255k versus about $213k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Implementation Silicon Correlation Engineer

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The CPU Implementation Silicon Correlation Engineer joins the hardware team to ensure that pre-silicon design targets for frequency, voltage, and power are successfully realized in final products across advanced technology nodes. The role involves performing data analysis using both pre-silicon and post-silicon data to establish silicon correlation. Key responsibilities include obtaining process-related measurement data from product and technology teams, analyzing timing runs to understand margins relative to measured parameters, evaluating the return on investment for design features with post-silicon teams, and analyzing speed debug data to root cause failing paths. Required skills include experience with chip tapeouts, STA, spice simulations, and data parsing or plotting. Preferred qualifications include knowledge of std cell architecture, device technology, ATPG patterns, PNR tool flows, and proficiency in TCL, Perl, and Python.

Skills

STA SPICE TCL Python Perl PnR ATPG Data Analysis Silicon Correlation Pre-silicon Design Post-silicon Debug tapeout

What you'll do

Analyze pre-silicon timing runs to understand margins and relate them to measured silicon parameters.
Perform data analysis using both pre-silicon and post-silicon data to establish silicon correlation to design targets.
Obtain process-related silicon measurement data from product and technology teams.
Evaluate the return on investment for specific design and methodology features with post-silicon teams.
Analyze post-silicon speed debug data to identify and root cause failing paths.
Ensure target frequencies, voltages, and power are realizable on silicon in final products.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience with a chip tapeout of a custom or PnR block.
Experience with Static Timing Analysis (STA).
Experience running spice simulations and analysis.
Skills in data parsing, analysis, and representation/plotting.
Chip design experience including CPU design (preferred).
Good understanding of std cell architecture and design (preferred).
Working knowledge of device technology, spice models, ATPG patterns, PNR tool flows, and TCL, Perl, or Python (preferred).