CPU Implementation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $184,700–$324,800 / yr
Posted: 16 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $220k

This role $255k

$131k most similar roles pay here $346k

This role pays more than 90% of similar roles. Most pay $184,900–$254,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $220k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Implementation Engineer

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As a CPU Implementation Engineer within the Silicon Engineering Group, you will drive block-level implementation and RTL-to-GDS design convergence. You will collaborate with micro-architects to define micro-architecture and evaluate power, performance, and area trade-offs while working with custom IP teams to co-optimize memory macros and library standard cells. Your daily responsibilities include managing backend flows, electrical requirements, silicon yield improvements, and coordinating with cross-functional teams on floorplanning, timing, and reliability. The role requires expertise in logic design, digital circuits, and high-frequency, low-power design techniques. You will utilize industry-standard synthesis, PnR, STA, and power analysis tools to resolve complex designs. Proficiency in TCL or Perl is required to navigate the technical challenges of high-performance CPU microprocessor architecture and memory sub-systems within deep sub-micron technology environments.

Skills

RTL Synthesis PnR STA TCL Perl Digital Circuits floor-planning Physical Design Power Analysis Memory Macros Standard Cells Logic Design

What you'll do

Define micro-architecture and evaluate PPA trade-offs in collaboration with micro-architects.
Drive RTL-to-GDS design convergence through synthesis and place-and-route optimizations.
Deliver block-level designs while closing backend flows, electrical requirements, and silicon yield.
Collaborate with CAD and PD teams to optimize industry-standard synthesis and PNR tool features.
Coordinate with cross-functional teams on CPU floorplanning, timing, power, reliability, and testability.
Co-optimize memory macros and library standard cells with custom IP teams to improve design PPA.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience in logic design and digital circuits.
Experience with low power and high frequency design techniques.
Experience with TCL or Perl.
Familiarity with high performance CPU microprocessor architecture and memory sub-system (preferred).
Knowledge in deep sub-micron technology and its implications to timing, power, and area (preferred).
Proficiency in industry standard logic Synthesis, PnR, STA, and Power analysis tools (preferred).
Excellent communication and interpersonal skills (preferred).