Wireless Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k

This role $174k

$116k most similar roles pay here $232k

This role pays more than 55% of similar roles. Most pay $159,000–$205,000 — the shaded band above. At the midpoint, this role pays about $174k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Wireless Design Verification Engineer

Apply Now Log in to save

As a Wireless Design Verification Engineer at the senior level within our cutting-edge wireless product team, you will play a pivotal role in ensuring the success of multi-gigabit wireless technology by developing sophisticated verification methodologies. Your daily responsibilities include owning the entire verification process from planning to closure, creating comprehensive UVM testbench environments and constrained random scenarios for complex protocols and datapaths, and collaborating with cross-functional teams to define verification strategies. You will leverage Python or Bash scripting for automation and enhance simulation infrastructure while addressing coverage gaps and resolving issues to drive feature closure. This role demands expertise in ASIC verification, digital IP development, and a strong understanding of functional coverage analysis and RTL simulation workflows.

Skills

UVM Python Perl Bash SystemC DPI UPF RTL Simulation CI/CD Linux

What you'll do

Own the entire verification process from planning to feature closure.
Develop UVM testbench environments and BFMs across block to system levels.
Implement constrained random scenarios for complex protocol functionality testing.
Track regression metrics, resolve issues, and address coverage gaps continuously.
Collaborate with Systems and Design teams to define comprehensive verification strategies.

What we're looking for

Extensive experience in ASIC verification or complex digital IP development.
Expertise in developing comprehensive UVM testbench environments and constrained random scenarios.
Proficiency in functional coverage analysis, RTL simulation workflows, and tracking regression metrics.
Strong collaboration skills for defining verification strategy with cross-functional teams.
Experience with bus functional models, transaction-modeling, and assertions.

Save