Wireless Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 60% of similar roles. Most pay $159,000–$205,000 — the shaded band above. At the midpoint, this role pays about $165k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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As a Wireless Design Verification Engineer at the senior level within our cutting-edge wireless product team, you will be responsible for ensuring the success of silicon designs through comprehensive verification methodologies. Your daily tasks include developing sophisticated UVM testbench environments and BFMs across various levels from block to system, implementing constrained random scenarios to exercise complex functionalities, and tracking regression metrics to drive closure on features. You will collaborate closely with cross-functional teams to define verification strategies and enhance simulation infrastructure automations, leveraging your expertise in ASIC verification and digital IP development. Proficiency in Python or Bash scripting for automation is preferred, as well as experience with power-aware simulations and system-level modeling approaches, all while contributing to the advancement of multi-gigabit wireless technology at scale.

Skills

UVM Python Perl Bash SystemC DPI UPF RTL SV Linux

What you'll do

Own the entire verification process from planning to feature closure.
Develop UVM testbench environments and BFMs across block to system levels.
Implement constrained random scenarios for complex protocol functionality testing.
Track regression metrics, resolve issues, and address coverage gaps continuously.
Collaborate with Systems and Design teams to define comprehensive verification strategies.

What we're looking for

Extensive experience in ASIC verification or complex digital IP development.
Expertise in developing comprehensive UVM testbench environments and constrained random scenarios.
Proficiency in functional coverage analysis, RTL simulation workflows, and regression metric tracking.
Strong problem-solving skills with a collaborative approach to engineering challenges.
Experience with bus functional models, transaction-modeling, and assertions.

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