Timing Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $242k

$131k $327k

below market most similar roles pay here above market

This role pays more than 79% of similar roles. Most pay $168,425–$241,750 — the blue band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Timing Design Engineer

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The Timing Design Engineer joins a multifaceted group to support PHY design efforts by collaborating with architecture, CAD, and logic design teams. This role focuses on timing sign-off, developing STA and sign-off flows, and owning IP and block level timing constraints from synthesis to sign-off. The engineer will interact with RTL designers to understand design intent and clock structures while working with physical design teams to achieve sign-off quality timing constraints. Key responsibilities include innovating timing constraints to mitigate pessimism and managing signal integrity issues. Required technical skills include expertise in Primetime STA tools, SDC constraints generation, and proficiency in Tcl and Perl scripting. The role addresses critical timing closure and physical design challenges within the ASIC design flow for high-performance hardware products.

Skills

STA Timing Closure Primetime SDC Tcl Perl ASIC Design Synthesis DFT Physical Design Signal Integrity RTL Clock Structure

What you'll do

Perform timing sign-off and manage timing closure for SoC designs.
Develop and maintain STA and sign-off flows.
Own IP and block-level timing constraints from synthesis through sign-off.
Collaborate with RTL designers to define design intent and clock structures.
Work with CAD teams to develop and optimize design flows.
Coordinate with physical design teams to achieve sign-off quality timing.
Create plans and methods to verify timing constraints.
Innovate timing constraints and flows to reduce pessimism and analysis fallouts.

What we're looking for

BS degree in a technical discipline.
Minimum 10 years of meaningful experience.
Thorough knowledge of the ASIC design timing closure flow and methodology (preferred).
At least 5+ years of experience in writing ASIC timing constraints and timing closure (preferred).
Expertise in STA tools (Primetime) and flow, timing corners/modes, process variations, and signal integrity issues (preferred).
Hands-on experience in timing/SDC constraints generation and management (preferred).
Proficiency in scripting languages such as Tcl and Perl (preferred).
Familiarity with synthesis, DFT, and backend related methodology and tools (preferred).

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