Timing Design Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 40 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 96% of similar roles. Most pay $168,425–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Timing Design Engineer

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The Timing Design Engineer joins the hardware team as an ASIC STA Engineer to manage all aspects of SoC design regarding timing. The role involves performing timing sign-off, developing STA and sign-off flows, and owning IP and block level timing constraints from synthesis through to final sign-off. The engineer must collaborate with RTL designers to understand design intent and clock structures, work with CAD to develop flows, and coordinate with physical design teams to close timing. Key responsibilities include innovating timing constraints to mitigate pessimism and managing signal integrity issues. Required expertise includes ASIC design timing closure methodology, Primetime tools, and SDC constraints generation. Proficiency in Tcl and Perl scripting is necessary, along with familiarity with synthesis, DFT, and backend related methodologies and tools.

Skills

STA ASIC Design Primetime Tcl Perl SDC Synthesis DFT Physical Design Timing Closure Signal Integrity RTL SoC Design

What you'll do

Perform timing sign-off for SoC designs.
Develop STA and sign-off flows.
Own IP and block level timing constraints from synthesis to sign-off.
Interact with RTL designers to understand design intent and clock structures.
Collaborate with CAD teams to develop and understand design flows.
Work with physical design teams to close and sign-off timing.
Create plans to verify timing constraints.
Innovate timing constraints and flows to mitigate pessimism or analysis fallouts.

What we're looking for

BS degree in a technical discipline.
Minimum 10 years of relevant experience.
Proven knowledge of the ASIC design timing closure flow and methodology (preferred).
2+ years of experience in writing ASIC timing constraints and timing closure (preferred).
Expertise in STA tools (Primetime), timing corners/modes, process variations, and signal integrity issues (preferred).
Hands-on experience in timing/SDC constraints generation and management (preferred).
Proficiency in scripting languages such as Tcl and Perl (preferred).
Familiarity with synthesis, DFT, and backend related methodology and tools (preferred).

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