System Performance Modeling Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
59 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 10, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k
This role $144k
$103k most similar roles pay here $234k

This role pays less than 80% of similar roles. Most pay $151,528–$214,000 — the shaded band above. At the midpoint, this role pays about $144k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · System Performance Modeling Engineer

The System Performance Modeling Engineer joins the Infrastructure IP Team to focus on system and platform architecture, specifically regarding Network-on-Chip (NoC) topology and system memory architecture. You will perform architecture-oriented performance and power explorations for components like system caches, memory controllers, and interconnects using cycle-accurate and approximate models. Day-to-day responsibilities include analyzing complex datasets to identify bottlenecks, developing new tools for architecture validation, and supporting exploratory projects involving machine learning and data science. The role requires proficiency in C++ and Python, a strong understanding of computer architecture, and knowledge of protocols like AHB, AXI, and ACE. You will work on the technical challenge of defining hardware modeling semantics and optimizing memory organization, address mapping, and interleaving to shape next-generation SoC designs while balancing performance, power, and area trade-offs in high-performance infrastructure components.

What you'll do

  • Conduct NoC topology and system memory architecture exploration campaigns to define requirements for next-generation SoCs.
  • Perform performance and power modeling for platform components including NoC, memory subsystems, and system caches.
  • Develop new tools for architecture validation, focusing on performance, power, and high-level functional verification.
  • Analyze complex datasets to identify patterns and insights for infrastructure hardware design decisions.
  • Support exploratory methodology projects involving machine learning and data science techniques.
  • Maintain and document innovative modeling frameworks while defining new hardware modeling semantics.

What we're looking for

  • A Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design experience.
  • A Master's degree in Science, Engineering, or a related field with 1+ year of ASIC design experience.
  • A PhD in Science, Engineering, or a related field.
  • Proficiency in Object-Oriented Programming using C++ and Python.
  • Experience in SoC modeling, software development, or data science and machine learning.
  • Knowledge of NoC architecture, memory hierarchy, and interconnect protocols like AHB/AXI/ACE/ACE-Lite.
  • Understanding of performance, power, and area trade-offs for system components like memory controllers and system caches.
  • Strong communication skills and the ability to adapt quickly to changes.

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