below marketmost similar roles pay hereabove market
This role pays less than
70%
of similar roles. Most pay
$142,500–$214,000
— the blue band above.
At the midpoint, this role pays about
$152k
versus about
$178k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The System Performance Modeling Engineer joins the Infrastructure IP Team to support the definition and design of platform hardware components like Interconnects, System Cache, Memory Controllers, and System MMUs. You will perform architecture-oriented performance and power explorations using cycle-accurate and approximate models to support micro-architecture optimizations and system-level decisions. Key responsibilities include conducting NoC topology and system memory architecture exploration campaigns, analyzing complex datasets to identify patterns, and developing new tools for architecture validation. You will utilize C++, Python, and knowledge of Object-Oriented Programming to maintain modeling frameworks and support exploratory methodology projects involving machine learning and data science. The role requires a deep understanding of computer architecture, memory hierarchy, and interconnect protocols like AHB, AXI, and ACE to solve complex hardware performance bottlenecks.
Conduct NoC topology and system memory architecture exploration campaigns to define next-generation SoC requirements.
Drive architecture-oriented performance and power explorations for NoC, memory subsystems, system caches, and memory controllers.
Develop new tools for architecture validation, specifically focusing on performance and power modeling.
Support exploratory methodology projects utilizing machine learning and data science techniques.
Expand, maintain, and document innovative hardware modeling frameworks.
Define new hardware modeling semantics that deviate from conventional hardware programming languages.
Analyze complex datasets to identify patterns and insights for platform-level architecture decisions.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
Robust understanding of computer architecture, memory hierarchy, and system/platform architecture.
Experience or knowledge in NoC architecture, topologies, and design trade-offs.
Strong knowledge of Object-Oriented Programming in C++ and Python.
Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite and NoC concepts.
CPU Architecture
C
C++
Python
Perl
RTL
SIMD
micro-architecture
Performance Modeling
OS Internals
Compiler Technology
Post-silicon Verification
Benchmarks
SoC Architecture
System Architecture
AI Accelerators
Generative AI
machine-learning
C++
Python
DRAM
HBM
LPDDR
DDR
GDDR
Ethernet
InfiniBand
RDMA
Hardware/Software Co-design
ISA Design
Microarchitecture
Performance Modeling
Chiplets
RAS
ECC
3D Integration
SystemC
C++
Python
ASIC
SoC
Simulation
Architecture Exploration
ARM Fast Models
ISA Modeling
OMNeT
High-Performance Computing
Data Center Infrastructure
Networking
Scripting