SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TX
Salary
$145,600–$218,400 / yr
Posted
12 days ago
Freshness
Confirmed live today
Closes
Apr 13, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $219k
This role $182k
$130k $293k
below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $188,562–$250,000 — the blue band above. At the midpoint, this role pays about $182k versus about $219k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

Role Posting Log in to save

The SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform) joins the System Validation & Emulation team to ensure end-to-end silicon quality for next-generation AI accelerator and compute platforms. This role involves developing performance validation plans, analyzing SoC bandwidth, QoS, latency, and throughput, and driving correlation between pre-silicon models and silicon measurements. You will evaluate AI inference and training workloads to optimize throughput and power-performance efficiency. Key technical requirements include expertise in NoCs, AXI, AHB, FIFO designs, memory hierarchy, and cache coherency. You must be proficient in C, C++, Python, and assembly to design drivers and test content. The work focuses on complex hardware and software debugging using JTAG, Perfmon architecture, and kernel debuggers to solve power and performance trade-offs.

Skills

SoC Validation ASIC Design Python C C++ Assembly NoC AXI AHB JTAG Perfmon Emulation Pre-silicon Post-silicon Cache Coherency DDR AI/ML Accelerators Kernel Debuggers FIFO

What you'll do

  • Develop thorough performance validation plans that factor in power-performance trade-offs.
  • Analyze SoC bandwidth, Quality of Service (QoS), latency, and throughput.
  • Write programs to stress interconnect transactions for appropriate coverage.
  • Debug complex hardware and software issues using JTAG-based debuggers and state dump scripts.
  • Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements.
  • Evaluate AI inference and training workloads for throughput, latency, and power efficiency.
  • Create performance dashboards, reports, and technical reviews for leadership and stakeholders.
  • Design and implement drivers and test content using C, C++, Python, and assembly.

What we're looking for

  • BS in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, or integration experience.
  • MS in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
  • 7+ years of experience in silicon validation or platform bring-up.
  • Expertise in interconnect architectures (NoCs, AXI, AHB), FIFO designs, memory hierarchy, caches, and CPU/DDR concepts.
  • Proficiency in C, C++, Python, and assembly languages for driver design and test content implementation.
  • Experience with JTAG debuggers, kernel debuggers, and Perfmon architecture for hardware/software co-optimization.
  • Knowledge of AI/ML workloads, tensor operations, and transformer models (preferred).

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