SoC Infrastructure/NoC, Power & Performance Validation Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday
Closes
Mar 23, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $152k
$107k most similar roles pay here $260k

This role pays less than 88% of similar roles. Most pay $168,400–$231,150 — the shaded band above. At the midpoint, this role pays about $152k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 568 open roles on FindRole.

Listed pay typically runs $150,615–$222,050 across 554 roles with salary data.

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At a glance

TL;DR · SoC Infrastructure/NoC, Power & Performance Validation Engineer

The SoC Infrastructure/NoC, Power & Performance Validation Engineer joins the Global SoC digital hardware organization to ensure silicon quality through pre-silicon emulation and post-silicon validation. This role involves developing content to validate and analyze SoC bus architecture, performance, and power while managing trade-offs between performance and power. The engineer will perform bandwidth, QoS, latency, and throughput analysis for interconnect architectures like NoCs, AXI, and AHB. Key responsibilities include validating system low power modes, dynamic clock and voltage scaling, interrupt architecture, and memory hierarchy consistency. Candidates must possess expertise in C, C++, Python, and assembly to develop drivers and test content while debugging low-level software and hardware issues using JTAG and kernel debuggers. The role requires deep knowledge of CPU, DDR, and GPU concepts alongside experience leveraging Generative AI technologies for workflow optimization.

What you'll do

  • Analyze SoC bus architecture performance, power, and bandwidth metrics including QoS, latency, and throughput.
  • Develop programs to stress interconnect transactions for NoC, AXI, and AHB architectures.
  • Create comprehensive performance validation plans that account for Power-Performance trade-offs.
  • Validate system low power modes and dynamic clock and voltage scaling operations.
  • Debug low-level hardware and software issues using JTAG tools and kernel debuggers.
  • Develop drivers and test content using C, C++, Python, and assembly languages.
  • Validate memory hierarchy features including cache coherency, consistency, and synchronization.
  • Utilize Generative AI technologies to optimize internal engineering workflows.

What we're looking for

  • Bachelor's degree in Science or Engineering with 2+ years of ASIC experience, Master's with 1+ year, or a PhD.
  • Experience in ASIC design, verification, validation, or integration.
  • Expertise in SoC bus architectures including NoC, AXI, and AHB.
  • Proficiency in C, C++, Python, and assembly languages for embedded systems.
  • Knowledge of SoC performance metrics such as bandwidth, QoS, latency, and throughput analysis.
  • Understanding of power management including low power modes, dynamic clock/voltage scaling, and semiconductor power types.
  • Experience with memory hierarchy, cache coherency, and hardware debug tools like JTAG.
  • Experience leveraging Generative AI technologies for optimizing workflows (preferred).

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