Staff SOC Mixed Signal Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$155,168–$210,000 / yr
Posted
30 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 8, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $183k
$144k most similar roles pay here $239k

This role pays less than 56% of similar roles. Most pay $170,000–$222,000 — the shaded band above. At the midpoint, this role pays about $183k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Staff SOC Mixed Signal Engineer

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The Staff SOC Mixed Signal Engineer joins the ASICS Engineering team to lead physical design implementation for complex blocks using advanced tools such as Cadence Innovus and Synopsis PTSI. This individual manages the development of IP cores on deep sub-micron technology nodes including 4nm and 3nm while overseeing the work of junior team members. Key responsibilities include developing implementation strategies, performing timing and power analysis, optimizing clock latencies, and conducting advanced power checks to ensure design specifications are met. The role requires collaborating with digital designers to debug timing and facilitate logic changes. Technical expertise is required to resolve complex implementation challenges and provide technical leadership during project reviews. The candidate will also be responsible for writing technical documentation and evaluating team workflows to improve overall efficiency in the physical design environment.

Skills

ASIC Cadence Innovus Physical Design Power Analysis Physical Verification ECO Digital Design IP Core 3nm 4nm Sub-micron Technology Technical Documentation

What you'll do

  • Execute advanced physical design implementation for complex blocks using Cadence Innovus and Synopsys PTSI tools.
  • Develop and implement IP designs using state-of-the-art tools on 4nm and 3nm technology nodes.
  • Perform deep analysis of clock and data path timing to identify and resolve critical issues.
  • Conduct advanced power checks on multiple blocks to ensure design specifications are met.
  • Optimize clock latencies for major clocks to reduce the design ECO cycle time.
  • Own the design and verification strategies for ASICs and IP cores while reviewing junior team members' work.
  • Write, review, and edit technical documentation for project reviews and internal meetings.
  • Act as a technical lead on projects by owning deliverables and communicating development plans.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Two years of experience in a related occupation.
  • Experience using tools such as Cadence Innovus and Synopsys PTSI for physical design.
  • Expertise in advanced architecture and implementation in deep sub-micron technology nodes (4nm, 3nm).
  • Ability to perform complex timing, power analysis, and physical verification.
  • Proficiency in developing implementation strategies that meet system requirements and customer needs.
  • Experience performing advanced power checks and interpreting results of highly complex performance checks.
  • Ability to write, review, and edit technical documentation for design or project reviews.

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