Senior Mixed Signal Design Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 178 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $177k

$126k most similar roles pay here $228k

This role pays less than 51% of similar roles. Most pay $167,300–$214,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Mixed Signal Design Engineer

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As a Senior Mixed Signal Design Engineer within the Mixed-Signal high-speed I/O SerDes group, you will develop critical intellectual property for complex SoCs supporting standard and proprietary high-speed protocols. You will collaborate with analog designers to create accurate SystemVerilog models for components like closed-loop PLLs, Rx CTLE, SAR ADCs, and optics. Working alongside system architects and digital designers, you will define and verify system architecture specifications while refining adaptation algorithms such as DFE, CTLE, CDR, and offset cancellation. Your daily responsibilities include streamlining workflows through Perl and Python scripting to improve efficiency and reusability, as well as participating in silicon bringup by creating scripts for debug, QA, characterization, and ATE. You must possess expertise in Verilog, SystemVerilog, logic design, circuit modeling, and high-speed Serdes/PLL analog circuit design.

Skills

SystemVerilog Verilog Mixed-Signal Design SerDes PLL ADC CTLE CDR DFE Python Perl FPGA SATA PCIe USB Circuit Modeling Scripting Silicon Bringup ATE

What you'll do

Create accurate SystemVerilog models for analog components like PLLs, Rx CTLE, SAR ADCs, and optics.
Define and verify system architecture specifications in collaboration with architects and digital designers.
Refine adaptation algorithms for mixed-signal blocks including DFE, CTLE, CDR, and offset cancellation.
Develop scripts to streamline workflows and increase design reusability.
Participate actively in silicon bringup processes.
Create scripts for debug, QA, characterization, and ATE testing.

What we're looking for

B.S. or MS degree in Electrical Engineering or equivalent experience.
5+ years of experience working in high-speed I/O digital design.
Knowledge at the protocol level (SATA, PCIe, USB) is preferred.
Deep understanding of Verilog or SystemVerilog, logic design, and circuit modeling for mixed-signal blocks.
Deep understanding of high-speed Serdes/PLL analog circuit design.
Proven experience with custom digital circuit design and adaptation algorithms like DFE, CTLE, CDR, and offset cancellation.
Strong background in Perl and Python scripting.
FPGA emulation experience is a plus.

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