STA Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$153,200–$229,800 / yr
Posted
66 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 3, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $158k
This role $192k
$115k most similar roles pay here $242k

This role pays more than 78% of similar roles. Most pay $129,243–$186,900 — the shaded band above. At the midpoint, this role pays about $192k versus about $158k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · STA Engineer

Role Posting Log in to save

STA Engineer As a member of the Integrated Wireless Technology team, the STA Engineer will lead static timing closure and synthesis for complex low-power Wi-Fi SoCs and sub-systems. The role involves driving timing-critical implementation for high-performance connectivity chipsets across mobile, automotive, and IoT platforms. Day-to-day responsibilities include performing pre-layout and post-layout timing analysis, identifying bottlenecks, developing SDC constraints, and managing multi-corner, multi-mode runs. The engineer will also perform synthesis, formal verification, and low-power checks while balancing power, performance, and area constraints. Key technical requirements include proficiency in Synopsys PrimeTime, Design Compiler, or Cadence Genus, along with scripting skills in TCL, Perl, and Python. The role addresses the challenge of delivering high-quality silicon on aggressive schedules for next-generation wireless products by providing actionable timing feedback and implementing functional ECOs to ensure robust design integrity.

Skills

Static Timing Analysis Synthesis SDC TCL Perl Python Synopsys Prime Time Synopsys Design Compiler Cadence Genus Conformal ECO UPF LEC MMMC CDC AXI AHB PCIe USB

What you'll do

  • Drive subsystem-level and full-chip static timing analysis (STA) for pre-layout and post-layout phases.
  • Identify timing bottlenecks and provide micro-architectural or implementation-level optimizations to resolve violations.
  • Develop, validate, and maintain SDC constraints for multi-mode and multi-corner (MMMC) environments.
  • Perform synthesis, formal verification (LEC), and low-power checks for complex SoCs and sub-systems.
  • Manage I/O timing budgets and provide actionable feedback for root cause analysis and ECO guidance.
  • Balance Power, Performance, and Area (PPA) constraints during the implementation process.
  • Execute functional and conformal ECOs to ensure design integrity.
  • Develop automated scripts using TCL, Perl, or Python to enhance STA and synthesis workflows.

What we're looking for

  • Bachelor's degree with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years in ASIC design or related fields.
  • 6 to 8 years of experience in ASIC/SoC STA, synthesis, timing constraint development, and functional ECO implementation.
  • Deep knowledge of Static Timing Analysis (STA), MMMC timing closure, OCV/AOCV/POCV, and advanced technology nodes.
  • Experience with Synthesis, Logical Equivalence Checking (LEC), and low-power design techniques including multi-voltage designs and UPF.
  • Proficiency in scripting using TCL and Perl to automate STA and synthesis flows.
  • Hands-on experience with Synopsys PrimeTime and Synopsys Design Compiler or Cadence Genus.
  • Familiarity with wireless SoC design, peripheral interfaces like PCIe/USB, and power estimation tools like PrimePower.

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