ASIC Design STA Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
147 days ago
Freshness
Confirmed live yesterday
Closes
Apr 17, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $208k
$141k most similar roles pay here $261k

This role pays more than 57% of similar roles. Most pay $175,000–$224,150 — the shaded band above. At the midpoint, this role pays about $208k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC Design STA Engineer

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The ASIC Design STA Engineer joins the team to support the development of large SoCs featuring multiple physical blocks and over 300 clock domains. The role involves building and verifying timing constraints for intricate designs, implementing pre-route timing checks, and performing quality of results cleanup to ensure high-quality handoffs for static timing analysis. Key responsibilities include developing multi-mode and multi-corner timing constraints, maintaining RTL quality metrics in hierarchical designs, and automating these processes for efficiency. The position requires expertise in SDC development, EDA tool proficiency, and Tcl-based scripting within both standalone Linux environments and specific tools like Synopsys Design Compiler and Primetime. Candidates will also collaborate with CAD teams to develop pre-production synthesis and STA workflows while utilizing tools such as Spyglass and Fishtail to resolve complex design and constraint issues.

Skills

STA SDC TCL Synopsys Design Compiler PrimeTime RTL Synthesis P&R EDA Tools Spyglass Fishtail Linux QoR Scripting ASIC Design

What you'll do

  • Develop complex multi-mode and multi-corner timing constraints compatible with both RTL and signoff requirements.
  • Maintain and automate RTL quality metrics for large, hierarchical SoC designs to improve process efficiency.
  • Perform pre-route timing checks and Quality of Results (QoR) cleanup to ensure high-quality handoffs for STA.
  • Develop Tcl-based scripts for use in both standalone Linux environments and specific EDA tool flows.
  • Collaborate with CAD teams to develop pre-production synthesis and Static Timing Analysis workflows.
  • Analyze timing reports to identify and resolve design-related and constraint-related issues.
  • Create custom Tcl Quality Control (QC) and QoR checks using specific tool attribute queries.

What we're looking for

  • Bachelor's or Master's degree in computer engineering, electrical engineering, or a related field.
  • Expertise in SDC development and debugging for complex, hierarchical designs.
  • Proficiency in EDA tools including Synopsys Design Compiler, Primetime, Spyglass, and Fishtail.
  • Ability to develop complex TCL scripts for both standalone Linux environments and within EDA tools.
  • Experience building timing constraints for IPs, blocks, and full-chip implementations in flat and hierarchical flows.
  • Experience analyzing timing reports to identify design and constraint-related issues.
  • Proficiency in both front-end (RTL) and back-end (Synthesis and P&R) processes.
  • Strong analytical, problem-solving, and communication skills.

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