STA Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 144 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $158k

$121k most similar roles pay here $198k

This listing doesn't post a salary. Most similar roles pay $129,575–$186,975.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · STA Engineer

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As an STA Engineer, you will join a dynamic team focused on leading edge IP development and coordinating with multiple SOC teams. You will be responsible for full chip and block level timing closure and constraints ownership throughout the entire project lifecycle. Your daily work involves collaborating with SoC Design, Verification, DFT, Architecture, and Physical Design specialists to execute design and integration tasks for high quality IP deliverables. Additionally, you will partner with CAD and Flow teams to define and improve front-end design methodologies while developing and maintaining timing analysis flows. The role requires strong digital design fundamentals, familiarity with ASIC design timing concepts, and proficiency in scripting languages like TCL, Python, and Perl. You will also utilize STA tools such as Primetime to manage timing constraints, corners, and modes for complex hardware products.

Skills

STA ASIC Timing Closure TCL Python Perl Primetime Synthesis Logic Equivalence Check Digital Design SOC

What you'll do

Own full chip and block level timing closure and constraints throughout the project lifecycle.
Execute design and integration tasks for high-quality IP deliverables across multiple SoC teams.
Develop and maintain methodologies and flows specifically related to timing analysis.
Collaborate with CAD and Flow teams to define and improve front-end design methodologies.
Write and manage timing constraints using industry-standard tools like Primetime.
Perform timing analysis across various modes and corners for ASIC designs.
Coordinate with SoC Design, Verification, DFT, Architecture, and Physical Design teams.

What we're looking for

Bachelor's Degree is required.
Strong fundamentals in digital design are preferred.
Familiarity with ASIC design timing concepts is preferred.
Proficiency in scripting languages such as TCL, Python, and Perl is preferred.
Experience with STA tools like Primetime and knowledge of timing constraints and corners is a plus.
Familiarity with front-end tools and methodologies including Synthesis and Logic equivalence checks is preferred.
Ability to communicate effectively across all internal groups is required.