STA Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Austin, TX
Posted
52 days ago

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Salary context

How this pay compares to similar roles

Similar $159k
$117k most similar roles pay here $201k

This listing doesn't post a salary. Most similar roles pay $124,750–$193,000.

Based on 239 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

As an ASIC STA Engineer at Apple, you will join a dynamic team of problem solvers responsible for leading-edge IP development and coordinating with multiple SOC teams to execute design and integration tasks. Your day-to-day responsibilities include full chip and block level timing closure/constraints ownership throughout the project lifecycle, working closely with SoC Design, Verification, DFT, Architecture, and Physical Design teams. You will collaborate with CAD and Flow teams to define and enhance front-end design methodologies, develop and maintain timing analysis methodology and flows, and ensure high-quality IP deliverables. Preferred qualifications include strong digital design fundamentals, familiarity with ASIC design timing concepts, proficiency in scripting languages like TCL, Python, and Perl, exposure to STA tools such as Primetime, and the ability to communicate effectively across various internal groups.

What you'll do

  • Lead the development of leading-edge IP for high-quality SOC deliverables.
  • Own full chip and block level timing closure and constraints throughout project phases.
  • Collaborate with CAD and Flow teams to enhance front-end design methodologies.
  • Develop and maintain methodology and flows related to timing analysis and verification.
  • Work closely with SoC Design, Verification, DFT, Architecture, and Physical Design teams.

What we're looking for

  • Strong fundamentals in digital design and ASIC timing concepts.
  • Proficiency in scripting languages like TCL, Python, and Perl.
  • Experience with STA tools (Primetime) and writing timing constraints.
  • Knowledge of front-end design methodologies including synthesis and equivalence checks.
  • Self-motivated and able to communicate effectively across multiple teams.

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