STA Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $147,400–$272,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $159k

This role $210k

$107k most similar roles pay here $290k

This role pays more than 82% of similar roles. Most pay $124,750–$193,000 — the shaded band above. At the midpoint, this role pays about $210k versus about $159k for comparable roles.

Based on 239 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

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As an ASIC STA Engineer at Apple, you will join a dynamic team responsible for leading-edge IP development and SOC design. Your role involves full chip and block level timing closure ownership throughout the project lifecycle, developing methodologies for timing verification and generating constraints for both blocks and full chips. You will collaborate closely with multiple SOC teams to execute design and integration tasks, resolving complex timing issues in high-end mobile applications. Ideal candidates possess strong digital design fundamentals, experience with STA tools like Primetime, and familiarity with front-end tools such as Synthesis and Logic Equivalence Checks. Knowledge of timing corners/modes and signal integrity issues is beneficial, along with the ability to communicate effectively across various internal groups.

Skills

Primetime Synopsys Galaxy Constraint Analyzer Synthesis Logic Equivalence Checks CI/CD Python Perl C++ Tcl Unix/Linux VCS Verdi WaveFormer Pro Calibre Questa CDC PrimePower Tempus Redhawk ICC2 PT-RCX

What you'll do

Lead full chip and block level timing closure throughout the project lifecycle.
Develop and maintain methodologies for timing verification and closure processes.
Generate comprehensive timing constraints for both blocks and full chips.
Collaborate with multi-functional teams to resolve complex SoC timing issues.
Work on high-end mobile application SoCs in deep sub-micron technologies.

What we're looking for

Bachelor’s degree in Electrical Engineering or Computer Science with 3+ years of experience.
Strong understanding of digital design principles and ASIC timing concepts.
Experience with STA tools like Synopsys PrimeTime.
Familiarity with front-end EDA tools including synthesis and equivalence checking.
Ability to generate and debug block and full chip timing constraints.
Excellent communication skills for collaboration across multiple teams.

Remote

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