STA Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $159k

$117k most similar roles pay here $201k

This listing doesn't post a salary. Most similar roles pay $124,750–$193,000.

Based on 239 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

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As an ASIC STA Engineer at Apple, you will join a dynamic team responsible for developing leading-edge IP and collaborating with multiple SOC teams on design and integration tasks. Your day-to-day responsibilities include full chip and block level timing closure ownership throughout the project lifecycle, methodology development for timing verification, and generation of constraints for complex SoCs targeting high-end mobile applications. You will work closely with multi-functional teams to resolve intricate timing issues and ensure high-quality IP deliverables. Ideal candidates possess strong digital design fundamentals, experience with STA tools like Primetime, familiarity with front-end methodologies such as Synthesis and Logic Equivalence Checks, and the ability to communicate effectively across various internal groups.

Skills

Primetime Synopsys_GCA Synthesis Logic_Equivalence_Checks CI/CD Python Perl Tcl Unix VCS Verdi WaveFormer Timing_Corners Modes Process_Variations Signal_Integrity_Issues

What you'll do

Lead full chip and block level timing closure ownership throughout the project.
Develop and maintain methodologies for timing verification and closure processes.
Generate timing constraints for both block and full chip levels.
Collaborate with multi-functional teams to resolve complex timing issues in SoCs.
Work on Apple SoC chips using deep sub-micron technologies for high-end mobile applications.
Familiarize with STA tools like Primetime for efficient design execution.

What we're looking for

Bachelor’s degree in Electrical Engineering or Computer Science with 3+ years of experience.
Strong understanding of digital design principles and ASIC timing concepts.
Experience with STA tools like Synopsys PrimeTime.
Familiarity with front-end EDA tools including synthesis and logic equivalence checks.
Ability to generate and debug block and full chip timing constraints.
Knowledge of timing analysis, process variations, and signal integrity issues.
Excellent communication skills for collaboration across multiple teams.

Remote

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