Physical Synthesis Implementation Engineer

Qualcomm

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$98,500–$147,700 / yr
Posted
58 days ago
Freshness
Confirmed live yesterday
Closes
Jan 11, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $123k
$83k most similar roles pay here $246k

This role pays less than 92% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $123k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Physical Synthesis Implementation Engineer

As a Physical Synthesis Implementation Engineer within the ASICS Engineering group, you will perform digital synthesis and static timing analysis for complex digital designs. You will collaborate with design, verification, and physical design teams to ensure timing closure and design optimization while assisting in the development of synthesis and STA scripts and methodologies. Your daily work involves running low power checks, performing logic equivalency checks, and documenting results for cross-functional review. The role requires proficiency in EDA tools such as Synopsys Design Compiler or Cadence Genus, along with a solid understanding of VLSI concepts and digital design principles. You must be skilled in scripting languages including TCL, Perl, or Python to solve technical problems. This position focuses on the implementation of high performance, low power IP blocks and SoC designs for various products.

What you'll do

  • Perform digital synthesis and static timing analysis (STA) for complex digital designs.
  • Ensure timing closure and design optimization in coordination with design, verification, and PD teams.
  • Develop and maintain scripts and methodologies for synthesis and STA processes.
  • Analyze and resolve timing issues identified during the design cycle.
  • Run low power checks and logic equivalency checks on integrated circuits.
  • Participate in design reviews to provide feedback on timing and synthesis aspects.
  • Document and report synthesis and STA results, including key findings and recommendations.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Preferred Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • 0 to 1+ years of Hardware Engineering experience or related work experience.
  • Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar.
  • Basic understanding of digital design principles and VLSI concepts.
  • Understanding of scripting languages such as TCL, Perl, or Python.
  • Knowledge of static timing analysis and timing closure techniques.
  • Strong verbal and written communication skills to convey complex information.

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