STA & Custom Logic Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 12 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k

This role $177k

$114k $268k

below market most similar roles pay here above market

This role pays less than 67% of similar roles. Most pay $175,450–$233,012 — the blue band above. At the midpoint, this role pays about $177k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · STA & Custom Logic Design Engineer

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STA & Custom Logic Design Engineer The STA & Custom Logic Design Engineer joins the Analog/Mixed Signal Design team to develop best-in-class custom mixed-signal designs. This role involves performing timing analysis on custom design circuits, delivering timing views to integration teams, and developing custom logic design for mixed-signal chips. Key responsibilities include owning timing closure throughout the project cycle, implementing STA constraints from specifications, and performing block- and chip-level static timing and noise analysis. The engineer will design and characterize transistor- and gate-level custom digital circuits while collaborating with RTL and custom design teams. Required skills include proficiency in circuit modeling, SPICE models, and high-speed design for SerDes and ADC. Preferred technical expertise includes STA tools like NanoTime, PrimeTime, or Tempus, and scripting in Python, Tcl, or Perl.

Skills

STA Mixed-Signal Design SPICE Python Tcl Perl PrimeTime Tempus NanoTime SDC DFT SerDes ADC SRAM POCV Circuit Modeling RTL

What you'll do

Own custom design timing closure throughout the entire project cycle.
Develop and implement STA constraints based on provided specifications.
Perform block-level and chip-level static timing and noise analysis.
Design and characterize transistor-level and gate-level custom digital circuits.
Propose correct-by-construction designs and methodologies for timing changes.
Debug functional and testing issues for the design verification and DFT teams.
Develop and maintain CAD methodologies and flows for timing verification and closure.

What we're looking for

Minimum requirement of a bachelor's degree.
Master’s Degree with 3+ years of relevant industry experience (preferred).
Solid understanding of timing analysis concepts including setup/hold, POCV, constraints, and transistor-level delay characterization.
Experience in timing analysis and verification for high-speed designs such as SerDes and ADC.
In-depth knowledge and analytical understanding of mixed-signal design techniques.
Strong track record of delivering silicon IPs with design and verification.
Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
Experience with STA tools, SRAM design, and scripting languages like Python, Tcl, or Perl (preferred).