SoC Physical Design Engineer, STA/Timing

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $242k

$146k $326k

below market most similar roles pay here above market

This role pays more than 81% of similar roles. Most pay $177,250–$233,137 — the blue band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, STA/Timing

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The SoC Physical Design Engineer, STA/Timing will join the Physical Design team to manage the physical implementation of design partitions from netlist to tapeout for a highly complex SoC using state of the art process technology. The role involves working with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeout. Key responsibilities include performing deep analysis of timing paths, implementing timing infrastructure, and creating scripts and methodologies for analysis and runs. Candidates must possess programming skills in Perl and TCL, along with experience in large design STA and timing closure. The position requires expertise in sub-micron technologies, circuit modeling including SPICE models, and understanding noise, crosstalk, and OCV effects to solve complex timing issues.

Skills

STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout

What you'll do

Execute physical implementation of design partitions from netlist to tapeout for complex SoCs.
Debug design constraints and facilitate logic changes to improve timing performance.
Create and implement timing ECOs for project tapeouts.
Develop and maintain scripts and methodologies for analysis and automated runs.
Perform deep analysis of timing paths to identify and resolve key issues.
Implement and manage timing infrastructure for high-performance SoC designs.
Create technical documentation, guidelines, and specifications for the design process.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience with large design STA and Timing Closure.
Programming skills with Perl and TCL.
Hands-on experience in STA (preferred).
Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Proficiency in STA and methodologies for timing closure with understanding of noise, crosstalk, and OCV effects (preferred).
Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Familiarity with ECO techniques and implementation (preferred).