SoC Physical Design Engineer, STA/Timing

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $142,300–$263,300 / yr
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k

This role $203k

$128k most similar roles pay here $279k

This role pays less than 60% of similar roles. Most pay $177,250–$241,750 — the shaded band above. At the midpoint, this role pays about $203k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · SoC Physical Design Engineer, STA/Timing

Role Posting Log in to save

As an SoC Physical Design Engineer, STA/Timing, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs using state of the art process technology. You will work closely with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeouts. Your daily responsibilities include performing deep analysis of timing paths to identify key issues, creating documentation, and developing scripts and methodologies for analysis runs. The role requires proficiency in STA, circuit modeling including SPICE models, and understanding of noise, crosstalk, and OCV effects. You will utilize Perl and TCL for scripting while managing timing closure for large high-performance SoC designs in sub-micron technologies to solve critical timing infrastructure challenges within the physical design team.

Skills

STA Timing Closure Physical Design Perl TCL ECO SPICE Crosstalk OCV Circuit Modeling Netlist Tapeout

What you'll do

Execute the physical implementation of design partitions from netlist to tapeout for complex SoCs.
Perform deep analysis of timing paths to identify and resolve critical issues.
Develop and implement timing ECOs to ensure successful project tapeouts.
Create and maintain scripts and methodologies using Perl and TCL for analysis and runs.
Build and maintain the underlying timing infrastructure for the design process.
Collaborate with design teams to debug constraints and facilitate logic changes to improve timing.
Create technical documentation, guidelines, and specifications for the physical design team.

What we're looking for

Minimum BS degree and 3+ years of relevant industry experience.
Experience with large design STA and Timing Closure.
Programming skills in Perl and TCL.
Hands-on experience in STA (preferred).
Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Proficiency in STA, timing closure methodologies, and understanding of noise, crosstalk, and OCV effects (preferred).
Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Familiarity with ECO techniques and implementation (preferred).

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 16 days ago

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI CMOS ECO Tapeout Digital Logic Design

Save