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Active Keyword: Sr. Design Verification Engineer Remove filter Clear all

7 of up to 20 (filtered)

Senior Design Verification Engineer

Amd

Santa Clara, CA +1 4 days ago $141,760–$212,640
Actively hiring Confirmed live yesterday Posted this week High trust Below market
SystemVerilog UVM VCS Verdi DVE Python Tcl Make Perl Shell PCIe Ethernet DDR AXI DMA UPF Formal Verification FPGA HAPS C/C++
Hybrid
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Senior Staff Design Verification Engineer

Amd

San Jose, CA 12 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
DFT Verilog SystemVerilog ATPG Scan MBIST LBIST Boundary Scan UVM OVM RTL Design Static Timing Analysis Python Tcl Perl Shell Synopsys DFT Compiler TestMAX PrimeTime VCS Cadence tool s FPGA
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 64 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 64 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 64 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 64 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 82 days ago $159,200–$215,300
Actively hiring Confirmed live yesterday Trusted Above market
UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS
7+ yrs exp
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