Senior ASIC Design Engineer, Ethernet Switch & High-Speed I/O

Amd

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 115 days ago
Freshness: Confirmed live 2 days ago
Closes: May 19, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $250k

$134k most similar roles pay here $318k

This role pays more than 88% of similar roles. Most pay $172,375–$218,875 — the shaded band above. At the midpoint, this role pays about $250k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Senior ASIC Design Engineer, Ethernet Switch & High-Speed I/O

Role Posting Log in to save

As a SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O, you will join the NTSG ASIC Design Team to contribute to the design of high-performance network chips, specifically AINIC and DPU. Working within the front-end design and integration team, you will collaborate with architecture, IP, physical design, and product engineers to achieve first pass silicon success. Your daily responsibilities include Ethernet subsystem design and integration, switch fabric, buffer, and queue implementation, as well as front-end RTL design for high-speed I/O subsystems and post-silicon bring-up support. You will utilize SystemVerilog, Verilog RTL design, VCS simulation tools, and Perl, Python, or Shell scripting. The role requires expertise in Ethernet protocols, switch design, buffer and queue management, and SerDes architecture to solve complex networking challenges within high-performance chip environments.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

RTL Design SystemVerilog Verilog Ethernet SerDes VCS Python Perl Shell Scripting ASIC Design Switch Fabric Queue Management High-speed I/O Post-silicon Bring-up

What you'll do

Design and integrate Ethernet subsystems for high-performance network chips.
Implement switch fabric, buffer, and queue designs.
Perform front-end RTL design and integration of high-speed I/O subsystems.
Coordinate with architecture, IP, and physical design teams to ensure first-pass silicon success.
Provide post-silicon bring-up support and contribute to yield learning.
Develop and utilize scripts in Perl, Python, or Shell for design tasks.

What we're looking for

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
Experience with SystemVerilog and Verilog RTL design.
Proficiency in VCS simulation tools and Perl, Python, or Shell scripting.
Knowledge of Ethernet protocols and switch design.
Understanding of buffer and queue management.
Knowledge of high-speed I/O (SerDes) architecture, design, and verification.
Strong communication and problem-solving skills with a detail-oriented approach.

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