SOC Power Architecture Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$109,400–$164,200 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $137k
$91k $282k
below market most similar roles pay here above market

This role pays less than 93% of similar roles. Most pay $176,100–$233,050 — the blue band above. At the midpoint, this role pays about $137k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SOC Power Architecture Engineer

The SOC Power Architecture Engineer joins the Camera Engineering group to develop power optimized multi-media hardware and systems architecture for next generation SOCs. The role involves prototyping on target power optimization features, performing waveform analysis, and implementing models for power projections, validation, and architectural trade off analysis. Key responsibilities include establishing use-case and hardware core power targets and collaborating with hardware and software design teams to validate features from concept to implementation. Candidates must possess a foundation in electrical systems engineering, digital logic design, and ASIC implementation flows. Required expertise includes low power design, video encoder/decoder systems, camera systems, and power modeling, verification, and simulation tools. Experience with high level synthesis tools and machine learning workload analysis is also relevant for this position.

What you'll do

  • Prototype on-target power optimization features and perform waveform analysis.
  • Develop power-optimized multi-media hardware and systems architecture for next-generation SOCs.
  • Implement models for power projections, validation, and architectural trade-off analysis.
  • Establish specific use-case and hardware core power targets.
  • Implement and validate power features through various design stages from concept to production.
  • Perform competitive analysis and machine learning workload analysis.

What we're looking for

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
  • Solid foundation in Electrical Systems Engineering and Digital Logic Design.
  • Solid understanding of HW micro-architecture of digital systems and ASIC implementation flow from concept to production.
  • Knowledge of system level aspects of low power design and the ability to model and analyze power at system and core levels.
  • Experience with video encoder/decoder systems and architecture.
  • Experience with camera systems and architecture.
  • Experience in power modeling, verification, and simulation tools.
  • Experience with high level synthesis tools and flow.
  • Competitive analysis and Machine Learning workload analysis experience (preferred).

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