below marketmost similar roles pay hereabove market
This role pays less than
53%
of similar roles. Most pay
$181,795–$254,750
— the blue band above.
At the midpoint, this role pays about
$218k
versus about
$218k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$218,400
across 551 roles with salary data.
The SOC Power Architect joins the ASICS Engineering group to define, model, design, optimize, verify, validate, implement, and document IP development for high performance, low power products. The role focuses on developing next generation power and limits systems to overcome thermal and electrical constraints in compute intense HPC, AI, and automotive systems. You will define systems for maximum performance within power envelopes, including a fast DCVS system to support high frequency CPU, GPU, and NSP transient responses. Key responsibilities include managing power control architecture, micro architecture, and interactions with software and product teams. Required skills include experience with UPF, power domain crossing, low power design methodology, and clock domain crossing designs. Proficiency in Perl and Python scripting is required, while post-Si debug expertise is considered a plus.
Define, model, and design digital and analog IP for high-performance, low-power products.
Develop next-generation power and limits systems to manage thermal and electrical constraints.
Design a fast DCVS system to support high-frequency CPU, GPU, and NSP transient responses.
Optimize system performance to meet power envelopes with minimum software intervention.
Implement power domain crossing and low-power design methodologies using UPF.
Develop Perl and Python scripts to support design and verification workflows.
Perform post-Si debug to identify and resolve hardware issues.
Document IP development for block and SoC integration.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
10+ years of strong experience in power and limits system.
Familiarity with UPF and power domain crossing.
Experience in low power design methodology and clock domain crossing designs.
ASIC
Digital Logic Design
Electrical Systems Engineering
Power Modeling
High Level Synthesis
Machine Learning
Waveform Analysis
Simulation Tools
Verification
RTL
Netlist
Power Analysis
Power Artist
PrimeTime PX
VLSI
DVFS
Clock Gating
Power Gating
Multi-voltage Domain Design
CPU Microarchitecture
Silicon Validation
C-model
Power Estimation
AI Tools