This role pays more than
64%
of similar roles. Most pay
$175,000–$248,400
— the shaded band above.
At the midpoint, this role pays about
$230k
versus about
$212k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
618 open roles
on FindRole.
Listed pay typically runs
$145,200–$219,600
across 600 roles with salary data.
As a SOC Power Architect within the ASICS Engineering group, you will develop next-generation power and limits systems to address performance bottlenecks caused by thermal and electrical constraints in compute-intensive HPC, AI, and automotive systems. You will define, model, design, optimize, verify, validate, implement, and document IP development for high-performance, low-power products. Your daily work involves designing a fast DCVS system to support the transient response of high-frequency CPU, GPU, and NSP components while ensuring optimal performance within power envelopes with minimal software intervention. The role requires expertise in power control and limits architecture, microarchitecture, and cross-functional collaboration. Required technical skills include familiarity with UPF and power domain crossing, low power design methodology, clock domain crossing designs, and proficiency in Perl and Python scripting for automation and post-Si debug tasks.
Define, model, design, and optimize IP blocks and SoCs for high-performance products.
Develop next-generation power and limits systems to manage thermal and electrical constraints.
Design a fast DCVS system to support transient responses for high-frequency CPU, GPU, and NSP components.
Establish power and limit architectures that maximize performance while minimizing software intervention.
Manage all aspects of power control architecture and microarchitecture interactions with system and software teams.
Implement low-power design methodologies and manage power domain crossings using UPF.
Develop Perl and Python scripts to support design, verification, and automation tasks.
Perform post-silicon debug to identify and resolve hardware issues.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
10+ years of strong experience in power and limits system.
Familiarity with UPF and power domain crossing.
Experience in low power design methodology and clock domain crossing designs.
SoC Architecture
Semiconductor Power Architecture
Power Integrity
Signal Integrity
C
C++
Scripting
Emulation
Silicon Validation
Firmware
Software Engineering
PC Architecture
Simulation
Tape-out
Electrical Systems Engineering
Digital Logic Design
ASIC
Power Modeling
High Level Synthesis
Machine Learning
Camera Systems
Waveform Analysis
Simulation Tools
Verification
SoC Architecture
Micro-architecture
Network-on-Chip
ARM
RISC-V
C++
Python
Linux
RTOS
Front-end Design
Verification
Power Management
Memory Systems
PCIe
USB
Ethernet
Machine Learning
Simulation
Modeling
unit-testing