SoC Power Modeling Engineer

As a SoC Power Modeling Engineer within the Silicon Engineering group, you will design state-of-the-art ASICs and model power dissipation for various IPs including AI/ML accelerators, CPUs, Graphics, and memory caches. You will be responsible for modeling power delivery, establishing voltage-frequency operating points for DVFM states, and modeling power dissipation for specific customer use-cases. The role involves collaborating with architecture, thermals, PMIC, and system design teams to optimize leading edge chips for power efficiency. You will also partner with lab and silicon characterization teams to correlate models with hardware data. Required skills include an understanding of low-power digital design, on-die PDN electrical properties, power gating, and thermal control loops. Technical competencies include scripting, data analysis, EDA tools, VLSI design flow, CMOS technology, and physical design tools for power optimization.