SoC Power Modeling Engineer

As a SoC Power Modeling Engineer within the Silicon Engineering group, you will design state-of-the-art ASICs and focus on modeling power dissipation for various IPs including AI/ML accelerators, CPUs, Graphics, and memory systems. You will be responsible for establishing voltage-frequency operating points for DVFM states, modeling power delivery for specific customer use-cases, and correlating models to hardware data through collaboration with lab and silicon characterization teams. The role requires expertise in low-power digital design, electrical properties of on-die PDN, power gating, and thermal control loops. You will utilize scripting, data analysis, and EDA tools while applying knowledge of VLSI design flow and CMOS technology. This position addresses the critical challenge of optimizing power efficiency for mobile SoC designs by modeling peak current requirements and voltage-frequency points across multiple integrated components.