SoC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

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Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3523 open roles on FindRole.

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At a glance

TL;DR · SoC Design Verification Engineer

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The SoC Design Verification Engineer joins the Silicon Engineering Group to verify sophisticated SoCs driving a flagship Cellular 5G platform. This role involves integrating multiple IP-level verification environments, crafting highly reusable UVM test benches, and implementing coverage-driven test infrastructure. The engineer will develop AIML methodology, deploy new tools, and improve tape-out readiness for complex chips. Key responsibilities include building verification plans from specifications, creating portable test benches, and collaborating with architecture and software teams. Required skills include knowledge of object-oriented programming in languages like Python, C++, Java, or SystemVerilog, along with coursework in Digital Design. The role requires expertise in high-efficiency SoC architecture, including SPI, I2C, UART, DDR, PCIe, and low-power specs, while addressing technical challenges in multi-chip SoC debug architecture and cellular protocols.

Skills

SystemVerilog UVM Python C++ Digital Design SoC Architecture DV Methodology PCIe DDR SPI I2C UART AIML HVL Coverage-Driven Verification Multi-processor Systems Cellular 5G FW-HW Interactions

What you'll do

Build coverage-driven verification plans from specifications to achieve specific coverage targets.
Create IP-level module and sub-system verification plans, test benches, and sequences.
Architect highly reusable UVM-based test benches and integrate multi-instance VIPs.
Integrate and verify overall SoC designs by working with design, architecture, and software teams.
Develop and deploy AIML methodology and new tools to improve tape-out readiness.
Apply knowledge of high-efficiency SoC architectures, including DDR, PCIe, and low-power specs.
Work with DV methodology architects to continuously improve the verification flow.

What we're looking for

Minimum requirement of a bachelor's degree.
Demonstrated knowledge of object-oriented programming principles through coursework, research, or project experience in any OOP-based language.
Coursework in Digital Design.
MSEE, MSCS or beyond is preferred.
Coursework in Computer Architecture or Networking Protocol (preferred).
Hands-on experience developing UVM-based testbenches in SystemVerilog, demonstrating applied understanding of object-oriented programming (preferred).
Experience in Digital Design (preferred).
Experience in developing reference models of DUT and verification using HVL (preferred).

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