SoC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $201k

This role $177k

$116k $256k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $168,500–$234,462 — the blue band above. At the midpoint, this role pays about $177k versus about $201k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3523 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2731 roles with salary data.

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At a glance

TL;DR · SoC Design Verification Engineer

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As a SoC Design Verification Engineer within the Silicon Engineering Group, you will join a team developing sophisticated SoCs for a flagship Cellular 5G platform. Your primary responsibilities include integrating IP-level verification environments, crafting highly reusable UVM test benches, and implementing coverage-driven test infrastructure. You will build verification plans from specifications, develop portable test benches, and deploy AIML methodologies to ensure tape-out readiness. The role requires proficiency in SystemVerilog, Python, C++, or Java, along with knowledge of object-oriented programming and digital design. You will work on complex technical problems involving high-speed layered protocols, low-power architecture, and multi-processor systems. Key domain areas include DDR, PCIe, USB, SPI, I2C, and memory management schemes, as well as firmware-hardware interactions and multi-chip SoC debug architectures.

Skills

SystemVerilog UVM Python C++ Digital Design SoC Architecture PCIe DDR SPI I2C UART AIML HVL Object-Oriented Programming Memory Management low-power architecture

What you'll do

Build coverage-driven verification plans from specifications to achieve specific coverage targets.
Create IP-level module and sub-system verification plans, test benches, and sequences.
Architect highly reusable UVM-based test benches and integrate multi-instance VIPs.
Integrate and verify overall SoC designs by working with design, architecture, and software teams.
Develop and deploy AIML methodologies to improve the quality of tape-out readiness.
Implement and deploy new tools to enhance the verification flow.
Apply knowledge of high-efficiency SoC architectures, including peripherals, memory management, and low-power specs.

What we're looking for

Minimum requirement of a bachelor's degree.
Demonstrated knowledge of object-oriented programming principles through coursework, research, or project experience in any OOP-based language.
Coursework in Digital Design.
MSEE, MSCS or beyond is preferred.
Coursework in Computer Architecture or Networking Protocol (preferred).
Hands-on experience developing UVM-based testbenches in SystemVerilog, demonstrating applied understanding of object-oriented programming (preferred).
Experience in Digital Design (preferred).
Experience in developing reference models of DUT and verification using HVL (preferred).

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