SoC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $168,500–$233,050 — the blue band above. At the midpoint, this role pays about $255k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3523 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2731 roles with salary data.

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At a glance

TL;DR · SoC Design Verification Engineer

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JOB TITLE: SoC Design Verification Engineer The SoC Design Verification Engineer joins the Silicon Engineering Group to verify sophisticated SoCs for a flagship Cellular 5G platform. This role involves integrating IP-level verification environments, crafting reusable UVM test benches, and implementing coverage-driven test infrastructure. You will develop AIML methodology, build verification plans from specifications, and create portable test benches and sequences. Key responsibilities include verifying high-speed layered protocols, memory management schemes, and multi-processor systems. The position requires expertise in SystemVerilog, Python, C++, or Java, along with object-oriented programming principles and digital design experience. You will solve complex problems regarding low-power architecture, FW-HW interactions, and multi-chip SoC debug architecture. The work focuses on ensuring tape-out readiness for complex silicon by collaborating with architecture, software, and external IP delivery teams.

Skills

SystemVerilog UVM Python C++ Java Digital Design SoC Architecture PCIe DDR SPI I2C UART AIML HVL

What you'll do

Build coverage-driven verification plans from specifications to achieve specific coverage targets.
Create IP-level module and sub-system verification plans, test benches, sequences, and test infrastructure.
Architect highly reusable UVM-based test benches and integrate multi-instance VIPs into the SoC level.
Integrate multiple sophisticated IP-level DV environments and test suites to verify overall SoC design.
Develop and deploy AIML methodology and new tools to improve tape-out readiness.
Apply knowledge of high-efficiency SoC architecture, including peripherals, memory management, and low-power specs.
Work with DV methodology architects to continuously improve the verification flow.

What we're looking for

B.S. degree required.
10+ years of experience required.
Demonstrated knowledge of object-oriented programming principles and experience in an OOP-based language like Python, C++, Java, or SystemVerilog.
Digital Design experience.
MSEE, MSCS, or higher degree (preferred).
Coursework in Computer Architecture or Networking Protocol (preferred).
Hands-on experience developing UVM-based testbenches in SystemVerilog (preferred).
Experience developing Reference Models of DUT and verification using HVL (preferred).

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