SoC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

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Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3523 open roles on FindRole.

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At a glance

TL;DR · SoC Design Verification Engineer

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The SoC Design Verification Engineer joins the Silicon Engineering Group to verify sophisticated SoCs driving a flagship Cellular 5G platform. The role involves integrating multiple IP-level verification environments, crafting highly reusable UVM test benches, and implementing coverage-driven test infrastructure. Key responsibilities include building verification plans from specifications, developing portable test benches, and deploying AIML methodology to improve tape-out readiness. The candidate must utilize SystemVerilog, Python, C++, or Java while applying object-oriented programming principles. Technical requirements include experience with digital design, high-speed layered protocols, and low-power architecture. The work focuses on complex SoC architectures, including memory management schemes, DDR, PCIe, USB, and secured boot schemes, while managing firmware-hardware interactions and multi-chip SoC debug architectures to ensure high-quality silicon performance.

Skills

SystemVerilog UVM Python C++ Java Digital Design SoC Architecture DDR PCIe SPI I2C UART USB AIML HVL Coverage-Driven Verification FW-HW Interaction Multi-processor Systems Memory Controller

What you'll do

Build coverage-driven verification plans from specifications to achieve specific coverage targets.
Create IP-level module and sub-system verification plans, test benches, and portable test infrastructure.
Architect highly reusable UVM-based test benches and integrate multi-instance VIPs into the SoC level.
Develop and deploy AIML methodology and new tools to improve tape-out readiness.
Integrate and verify overall SoC design by working with design, architecture, software, and firmware teams.
Apply knowledge of high-efficiency SoC architectures, including memory management, low power specs, and high-speed protocols.
Work with DV methodology architects to continuously improve the verification flow.

What we're looking for

B.S. degree required.
10+ years of experience required.
Demonstrated knowledge of object-oriented programming principles and experience in an OOP-based language like Python, C++, Java, or SystemVerilog.
Digital Design experience.
MSEE, MSCS or beyond (preferred).
Coursework in Computer Architecture or Networking Protocol (preferred).
Hands-on experience developing UVM-based testbenches in SystemVerilog (preferred).
Experience in developing reference models of DUT and verification using HVL (preferred).

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