Signal Integrity Architect, PCIe/CXL

What you'll do

• Own end-to-end signal integrity analysis and design closure for PCIe Gen 6+ and CXL interfaces.
• Develop channel budgets, margin analyses, design rules, and signoff criteria for PCIe/CXL links.
• Provide technical guidance for REFCLK distribution, including jitter-budget and topology considerations.
• Manage SI integration for retimers and redrivers, including placement and system margin analysis.
• Build and maintain package-to-board and full-channel simulation models using S-parameter and IBIS-AMI methods.
• Provide actionable guidance for PCB stackups, materials, routing constraints, and component selection.
• Define validation methodologies and partner with engineers on measurement execution and lab correlation.
• Develop and automate analysis flows to improve productivity and accuracy of SI workflows.

What we're looking for

• Bachelor's degree in Engineering or related field with 8+ years of experience, Master's with 7+ years, or PhD with 6+ years.
• 10+ years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems.
• Expertise in transmission-line theory, S-parameters, jitter, equalization, and system-level optimization.
• Experience with PCIe/CXL channel modeling, REFCLK analysis, and retimer/redriver integration.
• Proficiency in tools such as ANSYS HFSS/SIwave, Cadence Sigrity, CST, ADS, or Synopsys HSPICE.
• Experience with electrical validation using oscilloscopes, VNAs, TDR systems, BERTs, and protocol analyzers.
• Proficiency in Unix/Linux environments and scripting for EDA workflow automation.
• Ph.D. degree (preferred); 15+ years of experience; and knowledge of PAM4 signaling or CXL physical-layer implementation (preferred).