Senior Signal and Power Integrity Engineer

Nvidia

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
71 days ago
Freshness
Confirmed live today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $177k
$126k $228k
below market most similar roles pay here above market

This role pays more than 52% of similar roles. Most pay $147,200–$215,312 — the blue band above. At the midpoint, this role pays about $177k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Signal and Power Integrity Engineer

The Senior Signal and Power Integrity Engineer joins a dynamic team to lead board and system SI design activities. This role involves PCB stack up design, material selection, design guide implementation, layout review, and post-layout analysis. The engineer will perform system-level signal integrity simulations for interfaces including PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, and USB while optimizing the Power Delivery Network on PCBs. Key responsibilities include collaborating with Package and PCB Design teams and performing TDR and VNA measurements for material characterization. Required skills include a deep understanding of electromagnetics, transmission line theory, and experience with HFSS, Sigrity, Hspice, and Cadence Allegro. The work focuses on solving high-speed electrical interface performance issues across product lines ranging from consumer graphics to self-driving cars and artificial intelligence.

What you'll do

  • Lead board and system signal integrity (SI) design activities and PCB stack-up design.
  • Perform system-level signal integrity simulations for PCIe, LPDDR/DDR/GDDR, MIPI, HDMI, and USB interfaces.
  • Analyze and optimize the Power Delivery Network (PDN) on PCBs.
  • Collaborate with Package and PCB Design teams to craft solutions for system SI/PI performance.
  • Support customer board designs in coordination with the Application Engineering team.
  • Conduct TDR and VNA measurements for package and PCB material characterization and model correlation.
  • Implement design guides and perform layout reviews and post-layout analysis.

What we're looking for

  • BS/MS in Electrical Engineering or equivalent experience.
  • Minimum 4 years of experience as an SI/PI engineer.
  • Good understanding of electromagnetics, channel components, and transmission line theory.
  • Experience with design and implementation of high-speed electrical interfaces like PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, or USB.
  • Hands-on experience with HFSS, Sigrity, Hspice, or similar industry-standard simulation tools.
  • Experience with Cadence Allegro PCB designer, Constraints Manager, or other PCB stack-up designer tools.
  • Understanding of impacts of high-volume PCB manufacturing on channel signal integrity.
  • Expertise in high-speed interface SI/PI designs on industry standard system platforms (preferred).

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