Signal Integrity Architect

What you'll do

• Own SI analysis, simulation, and design closure for CXL 2.0/3.0 interfaces including channel budget and margin analysis.
• Develop full-topology SI models and simulations for assigned high-speed interface domains across PCB and system levels.
• Perform SI analysis on 2.5D/3D structures to establish design guidelines for advanced packaging integration.
• Manage SI analysis and design guidelines for GPIO/LSIO interfaces including SPI, I3C, and proprietary parallel interfaces.
• Provide technical feedback on PCB stack-ups, routing constraints, via structure designs, and material selection.
• Create customer-facing SI collateral such as application notes, reference documentation, and simulation models.
• Develop design automation tools and methodologies to drive innovation in signal integrity design processes.
• Prepare and present technical reports regarding SI performance to stakeholders, engineering teams, and customers.

What we're looking for

• A Bachelor's degree in Engineering or a related field with 8+ years of experience, a Master's with 7+ years, or a PhD with 6+ years.
• 8+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems.
• Expertise in CXL 2.0/3.0 specifications, PCIe Gen5+ SerDes standards, and other multi-gigabit serial buses.
• Proficiency with EM simulation tools such as ANSYS HFSS, Cadence Sigrity, CST, Keysight ADS, or Synopsys HSPICE.
• Strong knowledge of SI fundamentals including PDN, EMIR, transmission line theory, S-parameters, and channel simulations.
• Experience in characterizing GPIO, LSIO, and low-speed interfaces like SPI and I3C.
• Proficiency in Unix/Linux environments and scripting with MATLAB, Perl, or Python.
• Knowledge of packaging and PCB technologies including 2.5D/3D structures and manufacturing processes.